lect4 - CSE261 Spring 2008 Objectives: To learn about the...

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Unformatted text preview: CSE261 Spring 2008 Objectives: To learn about the variety of ways in which a logic function can be represented how to analyze combinational logic circuits how to realize logic functions using available gates how to transform a word description into a logic function Combinational Analysis Review: Logic Circuit Logic Function Truth Table Analyze a combinational logic circuit by obtaining a formal description of its logic function Outputs of a combinational logic circuit depends only on its current inputs (not on history) Kinds of combinational analysis: exhaustive (truth table) algebraic (expressions) CSE261 Combinational Logic Design #1 #1 CSE261 Combinational Logic Design #2 #2 Example: I) A B (A + B) B) F (B C) Combinational Circuit Synthesis II) Truth Table 1. C Logic Function Logic Circuit III) A 0 1 2 3 4 5 6 7 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F 0 0 1 1 1 1 1 1 F = [(A + B) (B C)] B) FA,B,C= (2,3,4,5,6,7) IV) F = A'BC'+A'BC+AB'C'+AB'C+ABC'+ABC BC' +A' BC+AB' +AB' C+ABC' Logic Function: The canonical sum expression. The canonical product expression. The canonical Implementations: AND-OR and its equivalent NAND-NAND ANDNAND OR-AND and its equivalent NOR-NOR ORNORLogic Function minimization: simplifying the logic function to reduce the number of gates. Minimization methods: Using theorems Karnaugh map CSE261 Combinational Logic Design #4 #4 2. FA,B,C = (0,1) V) A B VI) F=A+B F 3. F = (A+B+C)(A+B+C') (A+B+C)(A+B+C' 4. CSE261 Combinational Logic Design #3 #3 Combinational Logic Design 1 CSE261 Spring 2008 Combinational-Circuit Design CombinationalSometimes you can write an equation or equations directly using `logic' (the kind in your brain). logic' Example (alarm circuit): ALARM = PANIC + ENABLE . EXITING' . SECURE' EXITING' SECURE' SECURE = WINDOW . DOOR . GARAGE ALARM = PANIC + ENABLE . EXITING' . (WINDOW . DOOR . GARAGE)' EXITING' GARAGE)' Example (cont.): Alarm-circuit transformation AlarmSum-of-products form Sum- of Useful for programmable logic devices Multiply out Corresponding circuit: CSE261 Combinational Logic Design #5 #5 CSE261 Combinational Logic Design #6 #6 Sum-of-products form Sum- of- NAND-NAND Implementation NANDF = XYZ + XYZ + XYZ (XYZ) (X Y Z) X Z X (XYZ) (X YZ X Z) F AND-OR AND- Y Z (XYZZ (X Y ) X F = [(XYZ) (XYZ) (XYZ)] [(X Z) Z) NAND-NAND NANDCSE261 Combinational Logic Design #7 #7 F = XYZ + XYZ + XYZ CSE261 Combinational Logic Design #8 #8 Combinational Logic Design 2 CSE261 Spring 2008 Product-of-sums form Product- of- NOR-NOR Implementation NORF = (X + Y + Z)(X + Y' + Z)(X' + Y + Z)(X' + Y + Z')(X' + Y' + Z') (X' (X' (X' X Y OR - AND Z NOR - NOR CSE261 Combinational Logic Design #9 #9 CSE261 Combinational Logic Design #10 #10 Minimization Example: Prime Number Detector Truth table canonical sum (sum of minterms) Example (cont.): Minterm list Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 N3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 N2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 N1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 N0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F 0 1 1 1 0 1 0 1 0 0 0 1 0 1 0 0 canonical sum F = N3N2N1N0 (1,2,3,5,7,11,13) = N3 '. N2 '. N1 '. N0 + N 3 '. N2 '. N1 . N0 ' + N 3 '. N2 '. N1 . N0 + N 3 '. N2 . N1 '. N0 + N 3 '. N2 . N1 . N0 + N 3 . N2 '. N1 . N0 + N 3 . N2 . N1 '. N0 F = N3N2N1N0 (1,2,3,5,7,11,13) CSE261 Combinational Logic Design #11 #11 CSE261 Combinational Logic Design #12 #12 Combinational Logic Design 3 CSE261 Spring 2008 Example (cont.): Algebraic simplification (T10) Visualizing T10 - Karnaugh Maps A representation of the truth table by a matrix of cells, where each cell corresponds to a minterm (or a maxterm) of the logic function. For n-variable function, we need 2n rows truth table and 2n cells. cells. The cell number is equivalent to the row number in the truth table. table. The truth table values are copied into their corresponding cells. cells. The cell arrangements help to identify the input variable redundancy X Y + X Y = X X Y + X Y = X F = N3N2N1N0 (1,2,3,5,7,11,13) = N3 '. N2 '. N1 '. N0 + N 3 '. N2 '. N1 . N0 + N 3 '. N2 . N1 '. N0 + N 3 '. N2 . N1 . N0 + ... = (N3'. N2'. N1'. N0 + N3'. N2'. N1. N0) + (N3'. N2. N1'. N0 + N3'. N2. N1'. N0) + ... = N 3 '. N2 '. N0 + N 3 '. N2 . N0 + ... Reduce number of gates and gate inputs CSE261 Combinational Logic Design #13 #13 CSE261 Combinational Logic Design #14 #14 Two-variable Karnaugh map TwoExample 1: F = XY + XY XY X Row 0 1 2 3 X 0 0 1 1 Y 0 1 0 1 F 0 0 1 1 1 Example 2: F = XY + XY X Row 0 X 0 0 1 1 Y 0 1 0 1 F 1 1 0 0 1 X 0 1 2 X 0 1 2 Y 0 0 Y 0 0 0 1 3 1 1 Y 1 2 3 1 1 3 0 0 Y 0 1 Simplification: F = X(Y + Y) = X1 = X X(Y Simplification: F = X(Y + Y) = X1 = X CSE261 Combinational Logic Design #15 #15 CSE261 Combinational Logic Design #16 #16 Combinational Logic Design 4 CSE261 Spring 2008 Three-variable Karnaugh map ThreeExample 3: Row 0 1 2 3 4 5 6 7 X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Karnaugh-map usage Karnaugh1. F = XYZ + XYZ + XYZ + XYZ XY XY Z 0 1 0 1 0 1 0 1 F 1 1 0 0 1 1 0 0 1 0 Plot 1s corresponding to minterms of function. Circle largest possible rectangular sets of 1s. 1s. XY Z 0 00 2 01 6 11 X 10 4 2. # of 1s in set must be power of 2 OK to cross edges Variable is 1 Variable is 0 include variable include complement of variable variable not included 1 1 3 0 7 0 5 1 1 Z 3. Read off product terms, one per circled set. 1 0 Y 0 Variable is both 0 and 1 4. 5. Circled sets and corresponding product terms are called `prime implicants' implicants' Minimum number of gates and gate inputs CSE261 Combinational Logic Design #18 #18 Simplification: F = XY(Z + Z) + XY(Z + Z) = XY + XY = (X + X)Y= Y XY XY )Y CSE261 Combinational Logic Design #17 #17 Example 1: Combining Two cells: I) Cells (0,1): X=Y=0; Z=0,1 (0,1): Product term: X'Y' Cells (4,5): X=1; Y=0; Z=0,1 (4,5): Product term : XY' XY' OR: II) Cells (0,4): Y=0; Z=0; X=0,1 (0,4): Product term: Y'Z' Cells (1,5): Y=0; Z=1; X=0,1 (1,5): Product term : Y'Z Z Z XY 00 0 1 0 2 01 6 7 11 X 10 4 Example 1 (cont.): XY Combining four cells III) Cells (0,1,4,5) (0,1,4,5) Z X=0,1; Z=0,1; Y=0 The product term: Y' 1 1 X 00 01 2 6 7 11 4 10 1 1 3 5 1 1 Y Z 0 0 1 1 3 5 1 1 Y Z 1 XY 00 0 1 0 2 01 6 7 11 4 10 The sum of products expression of F: From I) From II) From III) F =X'Y'+XY' or =X' +XY' F=Y'Z'+Y'Z or: F=Y' +Y' 1 1 3 5 1 1 CSE261 Combinational Logic Design #19 #19 1 F =Y' =Y' CSE261 Combinational Logic Design #20 #20 Combinational Logic Design 5 CSE261 Spring 2008 Example 2: Z Combine cells (0,2,6,4) (0,2,6,4) X=0,1; Y= 0,1; Z=0 Product Term: Z' Combine cells (4,5) (4,5) X=1; Y=0; Z=0,1 Product Term: XY' XY' F = XY'+Z' XY' +Z' XY 00 0 1 0 2 01 6 11 X 10 4 Exercise: X 00 0 1 0 2 01 6 11 4 10 1 1 3 1 7 1 5 1 1 Z XY Z 1 1 3 1 7 5 1 1 Y Y 1 1 Z The canonical sum is: F=X'Y'Z'+XYZ'+XY'Z'+XY'Z+XYZ' F=X' +XYZ' +XY' +XY' Z+XYZ' CSE261 Combinational Logic Design #21 #21 CSE261 Combinational Logic Design #22 #22 Definitions: 1. In Example 1: Z XY 00 0 0 2 01 6 11 X 10 4 A logic function P implies a logic function F if for every input combination for which P=1, then F=1 also. (P is an implicant of F) Any minterm or combination of minterms in the canonical sum expression is an implicant of the output function A prime implicant is a group of combined minterms that can't be can' combined with any other minterm or group of minterms minterms are unique (i.e at least one minterm is not contained in any in other prime implicant. A unique minterm is called an Essential 1-Cell 1A minimal sum of a logic function is a sum-of-products expression sum- offor F such that no sum-of-products expression for F has fewer product sum- ofterms. 2. Implicants X'Y'Z' XY' XY' 1 1 3 1 7 1 5 1 1 Z 1 3. Y 4. Essential prime implicant is a prime implicant in which one or more Prime Implicants XY' XY' Z' 5. Essential Prime Implicants XY' XY' Z' CSE261 Combinational Logic Design #24 #24 CSE261 Combinational Logic Design #23 #23 Combinational Logic Design 6 CSE261 Spring 2008 Example 3: Combining (0,2) Product term: X'Z' Combining (2,3) Product term: X'Y Combining (3,7) Product term: YZ XY Z 0 1 0 00 2 01 6 11 X 10 4 5 Example 3: The prime implicants: 1- (0,2) X'Z' 2- (0,4) Y'Z' Z XY 00 0 1 0 2 01 6 11 X 10 4 1 1 3 1 7 1 Y 1 Z 1 1 3 1 7 5 1 1 Y Largest possible set Unique minterm X'Z', X'Y, and YZ are prime implicants X'Z', YZ are essential prime implicants X'Y is non-essential prime implicant (redundant) because all its nonminterms are covered in the other essential prime implicants F= X'Z'+X'Y+YZ OR: F = X'Z'+YZ (the minimal sum of F) X' X' CSE261 Combinational Logic Design #25 #25 No ess 3- (2,3) X'Y en t ia lp r im ei 4- (3,7) YZ mp lica nt! 1 1 Z 6 -(5,7) XZ 5- (4,5) XY' XY' Two possible minimal sums: 1- Using the prime implicants 1,4,and 5; F= X'Z'+YZ+XY' X' +YZ+XY' 2- Using the prime implicants 2,3,and 6; F= Y'Z'+ X'Y+XZ Y' X' CSE261 Combinational Logic Design #26 #26 Example 4: F = (1,2,5,7) 1. Summary: Load the minterms and maxterms into the K-map by placing the 1's K1' and 0's in the appropriate cells. 0' Look for groups of minterms and write the corresponding product terms (the prime implicants): 2. The group size should be a power of 2. Find the largest groups of minterms first then find smaller groups groups of minterms until all groups are found and all 1-cells are covered. 1- 3. 4. Determine the essential prime implicants. implicants. Select all essential prime implicants and the minimal set of the remaining prime implicants that cover the remaining 1's. 1' Its possible to get more that one equally simplified expression if more than one set of the remaining prime implicants contains the same number of minterms. CSE261 Combinational Logic Design #28 #28 5. CSE261 Combinational Logic Design #27 #27 Combinational Logic Design 7 CSE261 Spring 2008 Four-variable Karnaugh map FourWX YZ 00 01 11 00 0 1 3 2 4 5 7 6 01 11 12 13 15 14 8 9 11 10 Example 4: Row 0 W 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 CSE261 Combinational Logic Design #30 #30 F= W'X'Y'Z'+ W'X'YZ'+ YZ' W'XYZ'+ XYZ' W'XYZ+ WX'Y'Z'+ WX' WX'YZ'+ WX' YZ' WXY'Z'+ WXY' WXYZ W 10 1 2 3 4 5 6 7 8 9 10 11 12 Z Y 10 X 13 14 CSE261 Combinational Logic Design #29 #29 15 Example 4 (cont.): WX Essential prime implicants: The product term: XZ The product term : X'Z' Y YZ 00 01 11 10 00 01 11 Example 5: W 10 WX Essential prime implicants: The product term: X'Z Z The product term : XZ' XZ' Y YZ 00 01 11 10 00 01 11 W 10 1 1 1 1 X 1 1 1 1 1 1 1 1 X 1 1 1 1 Z F = XZ + X'Z' X' CSE261 Combinational Logic Design #31 #31 F = X'Z + XZ' XZ' CSE261 Combinational Logic Design #32 #32 Combinational Logic Design 8 CSE261 Spring 2008 Exercise: Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 W 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F 1 1 1 0 1 1 1 0 1 1 0 0 1 1 1 0 CSE261 Combinational Logic Design #33 #33 Exercise (cont.): W 00 00 01 11 0 1 3 2 4 5 7 6 01 11 12 13 15 14 8 9 11 10 10 WX YZ 00 01 00 0 1 3 2 01 4 5 7 6 11 12 13 15 14 W 10 8 9 WX YZ 1 1 1 1 1 1 1 1 Z Z 11 11 10 Y 10 Y 10 1 1 1 X X F = Y' + W'Z' + XZ' Y' W' XZ' CSE261 Combinational Logic Design #34 #34 Example 6: The prime implicants: W'X' W'Y' W'Z XYZ WXY The essential prime implicants: Y W'X' W'Y' WXY Cell 7 is not covered by any of the essential prime implicants. Its covered by two non-essential prime nonimplicant. We choose the one with the less number of variables which is W'Z W' WX YZ 00 01 11 10 00 0 1 3 2 01 4 5 7 6 11 12 13 15 W 10 8 9 11 10 Exercise: FW,X,Y,Z= (0,1,2,3,4,6,7,8,9,12,14) 1 1 1 1 1 1 1 Z 1 1 14 X F= W'X'+W'Y'+WXY+W'Z W' +W' +WXY+W' CSE261 Combinational Logic Design #35 #35 CSE261 Combinational Logic Design #36 #36 Combinational Logic Design 9 CSE261 Spring 2008 Five-variable Karnaugh map FiveFive variable K-map is formed using two connected four-variable maps: Kfourmaps: V VWX YZ 00 01 11 10 0 1 3 2 000 4 5 7 6 001 011 12 13 15 14 8 9 11 10 Cells (0,2,8,10) and (16,18,24,26) form essential prime implicant: X'Z' (0,2,8,10) (16,18,24,26) implicant: Cells(5,7,13,15) and (21,23,29,31) form essential prime implicant: XZ Cells(5,7,13,15) (21,23,29,31) implicant: F=XZ+X'Z' F=XZ+X' VWX YZ 000 00 0 4 001 011 12 13 W 010 8 100 16 101 20 21 V 111 28 29 W 010 100 16 17 19 18 101 20 21 23 22 111 28 29 31 30 W 110 W 110 24 Example 7: 24 25 27 26 1 1 3 2 5 9 1 1 7 1 17 19 18 1 25 27 26 01 11 Z 1 15 11 10 1 23 1 31 Z Y Y 10 1 6 1 14 1 22 1 30 1 X 1 1 X 1 CSE261 Combinational Logic Design #38 #38 X X CSE261 Combinational Logic Design #37 #37 Simplifying the Product of Sums 1. 2. Example 8: The prime implicants: Cells (0,1,8,9): X=0, Y=0 (0,1,8,9): The sum term: X+Y Plot 0s corresponding to maxterms of function. Circle largest possible rectangular sets of 0s. 0s. WX YZ 00 01 11 00 0 1 3 2 01 4 5 7 6 11 12 13 15 14 W 10 8 9 # of 0s in set must be power of 2 OK to cross edges Variable is 0 Variable is 1 include variable include complement of variable variable not included 0 0 0 0 0 Z 3. Read off product terms, one per circled set. Cells (8,10,12,14): W=1, Z=0 (8,10,12,14): The sum term: W'+Z 11 10 Y 10 Variable is both 1 and 0 0 0 4. 5. Circled sets and corresponding product terms are called `prime implicants' implicants' Minimum number of gates and gate inputs CSE261 Combinational Logic Design #39 #39 The two prime implicants are essential prime implicants and cover all zeros X The minimal product of sums: F = (X + Y) . (W' + Z) (W' CSE261 Combinational Logic Design #40 #40 Combinational Logic Design 10 CSE261 Spring 2008 Exercise: Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 W 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F 1 1 1 0 1 1 1 0 1 1 0 0 1 1 1 0 WX YZ 00 01 11 00 0 1 3 2 4 5 7 6 01 11 12 13 15 14 W 10 8 9 11 10 Simplifying POS - Another method Complement the function. Use K-map to get the minimal sum Kof the complement function. Complement the minimal sum to get the minimal product W WX 1. The function is complemented and represented using K-map: K2. The essential prime implicants are: WZ', X'Y WZ' X' YZ 00 01 11 00 0 1 3 2 01 4 5 7 6 11 12 13 15 14 10 8 9 Z Y 10 1 1 1 1 1 Z X Essential prime implicants: (3,7,15,11): Z=1, Y=1; The sum term: Z'+Y' +Y' (10,11): W=1, X=0,Y=1; The sum term: W'+X+Y' +X+Y' CSE261 #41 F=(Z'+Y').(W'+X+Y') Combinational Logic Design #41 F=(Z'+Y' ).(W' +X+Y' 3. The minimal Sum: M = X'Y' + WZ' Y X' WZ' 10 11 10 1 1 4. F = M' = (X'Y'+WZ')' = (X+Y).(W'+Z) M' (X' +WZ' (X+Y).(W' X CSE261 Combinational Logic Design #42 #42 Minimal Product of Sums vs. Minimal Sum of Products: Compare the minimal product and the minimal sum designs to find the best (least # of gates) realization. In the previous example: The minimal sum is: F = W'X + W'Y + XZ + YZ W' W' The minimal product: F = (X + Y) . (W' + Z) product: (W' The minimal product implementation is cheaper. Prime-number detector (again) Prime- CSE261 Combinational Logic Design #43 #43 CSE261 Combinational Logic Design #44 #44 Combinational Logic Design 11 CSE261 Spring 2008 Prime-number detector (cont.) PrimeWhen we solved algebraically, we missed one simplification -- the circuit below has three less gate inputs. Example 9: CSE261 Combinational Logic Design #45 #45 CSE261 Combinational Logic Design #46 #46 Example 10: Don't Care Conditions: Don' In some applications, the Boolean function for certain combinations of the input variables is not specified. The corresponding minterms (maxterms) are called "don't care don' minterms(maxterms)". minterms(maxterms)" In K-map , these are represented by `d'. KSince the output function for those minterms(maxterms) is not specified, those minterms(maxterms) could be combined with the adjacent 1 cells (0-cells) to get a more simplified sum-of(0sum- ofproducts (product-of-sums) expression. (product- ofCSE261 Combinational Logic Design #47 #47 CSE261 Combinational Logic Design #48 #48 Combinational Logic Design 12 CSE261 Spring 2008 Example 11: Build a logic circuit that determines if a decimal digit is 5 Example 11 (cont.): Truth Table Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CSE261 Combinational Logic Design #49 #49 W 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F 0 0 0 0 0 1 1 1 1 1 d d d d d CSE261 Combinational Logic Design #50 #50 1. 2. 3. 4. The decimal digits (0,1,2,...,9) are represented by 4 bit BCD code. code. The logic circuit should have 4 input variables and 1 output. output. There are 16 different input combinations but only 10 of them are used. The logic function should produce 0 if the number is < 5, and 1 if it is 5. 15 d Example 11 (cont.): K-Map K- Example 11 (cont.): Minimal Product WX 10 8 9 WX The Minimal Sum: Combining the `1' cells only, the minimal sum is: F = WX'Y'+W'XZ+W'XY WX' +W' XZ+W' Combining the dont care minterms with the `1' cells, the minimal sum is: YZ 00 01 11 00 0 1 3 2 4 5 7 01 11 12 13 15 W W 00 01 4 11 12 10 8 9 0 The Minimal Product: YZ 00 d d d d 1 1 F= (W+X).(W+Y+Z) Z Y 10 01 11 0 1 5 0 1 1 6 d d d d 1 1 Z 13 15 14 1 1 0 3 7 11 10 11 10 Y 10 d d 0 2 d d 6 1 14 0 1 F = W+XZ+XY X X CSE261 Combinational Logic Design #51 #51 CSE261 Combinational Logic Design #52 #52 Combinational Logic Design 13 CSE261 Spring 2008 Example 11 (cont.): Implementation The minimal sum implementation: F = W+XZ+XY W X Y Z F Multiple-Output Minimization MultipleMost digital applications require multiple outputs derived from the same input variables. X Y Z Logic Circuit F1 F2 The minimal product implementation: F= (W+X).(W+Y+Z) W X Y Z F W X Y Z F 1. Each output function could be minimized using K-map and Krealized independently. The output functions could share one or more product terms (prime implicant) which reduces the total number of gates. CSE261 Combinational Logic Design #54 #54 2. CSE261 Combinational Logic Design #53 #53 Example 12: F1 = XZ + YZ' YZ' F2 = XY' + YZ' XY' YZ' F1 Z 0 1 0 1 Example 12 (cont.): Logic Diagram F2 Z 10 4 0 1 5 0 1 XY 00 2 01 6 11 X 10 4 XY 00 2 01 6 11 X Independent realization Minimal realization F1= XZ+YZ' XZ+YZ' Z X Y Z F1 1 3 7 1 5 1 1 1 3 7 1 1 Y XY Z F2= XY'+YZ' XY' YZ' 1 Z Y F2 X 00 0 1 0 1 2 01 6 11 4 10 To find the common terms multiply the two functions (F1.F2) The common terms are: YZ', XY'Z YZ' XY' F1 X Y Z CSE261 Combinational Logic Design #56 #56 1 3 7 1 5 1 Y Z F2 CSE261 Combinational Logic Design #55 #55 Combinational Logic Design 14 CSE261 Spring 2008 Timing Hazards The Truth Table determines the Steady State behavior of a Combinational Logic Circuit Transient behavior: 1. 2. Definitions Static-1 Hazard: Two input combinations that: Static- Hazard: differ in only one variable. both produce logic 1. 1 0 Output could produce glitches when input variables change. Glitches occur when the paths between inputs and output have different delays. Timing Hazards refer to the possibility of having glitches during input transitions. possibly produce Logic 0 glitch during input variable transition Static-0 Hazard: Two input combinations that Static- Hazard: 3. differ in only one variable both produce logic 0 1 0 Hazards: 1. 2. 3. possibly produce Logic 1 glitch during input variable transition Definitions. Finding hazards. Eliminating hazards. CSE261 Combinational Logic Design #57 #57 Dynamic hazards: hazards: The output could change more than once during input transitions Caused by multiple paths with different delays from input to the output CSE261 Combinational Logic Design #58 #58 Example F = YZ + XZ' XZ' Delay in each gate is T . Input changes from XYZ = 111 to 110 Finding Timing hazards using K-map KAND-OR Circuits: ANDStatic 0 hazards do not exist in the sum-of products (AND-OR) implementation. sum(ANDStatic 1 hazards are possible The K-map of the function F in the previous example: KCell 6 and 7 are covered in two product terms. X Y Z Z' YZ XZ' XZ' F T glitch Y Z X F Faster Y Z X 1 1 0 0 1 1 0 Z 0 1 0 1 XY X 00 2 3 01 6 11 4 10 F 1 0 1 1 7 5 1 Z 1 Static 1 hazard CSE261 Combinational Logic Design #59 #59 1 Y 1 CSE261 Combinational Logic Design #60 #60 Combinational Logic Design 15 CSE261 Spring 2008 Timing hazards in OR-AND circuits OROR - AND Circuits: Static 1 hazards do not exist in the products-of sum (OR-AND) implementation. products(ORStatic 0 hazards are possible The minimal product of F = (X+Z)(Y+Z') (X+Z)(Y+Z' Cell 0 and Cell 1 are covered in two sum terms Static 0 hazard occurs when inputs switched between 000 to 001 Faster X Z Y 0 1 0 0 1 Z XY 00 0 1 0 2 01 6 11 4 5 Eliminating Timing Hazards AND-OR Circuit ANDAdd a prime implicant that combines the two inputs that cause static 1 hazard. XY X 00 01 2 3 6 11 4 10 0 1 Y Z X 10 1 1 0 1 1 0 F 1 0 1 1 Z 0 1 1 7 5 1 Z X 1 Y 1 F 0 1 0 1 0 0 1 3 0 7 0 0 Y 0 Z The hazard-free circuit hazard- Cells 6 & 7 are combined: XY Static 0 hazard CSE261 Combinational Logic Design #61 #61 CSE261 Combinational Logic Design #62 #62 Eliminating Timing Hazards OR - AND Circuit Add a prime implicant that combines the two inputs that cause static 0 hazard. XY Exercise F = W'X + Y'Z + WXYZ + WX'YZ' W' Y' WX' YZ' 1. W X Y Z W' W'X Y'Z X 00 01 2 6 11 4 5 10 0 Complete the timing diagram. (Assume all gates has same propagation delay=T ) Use K-map to show Static-0 hazards KStaticBuild a hazard-free circuit hazard- X Z Y 0 1 0 0 1 Z F 1 0 0 2. 3. 0 1 0 1 3 0 7 0 0 0 Y 0 Z WZYZ WX'YZ' WX' YZ' F T The hazard-free circuit hazard- Cells 0 & 1 are combined: X+Y CSE261 Combinational Logic Design #63 #63 CSE261 Combinational Logic Design #64 #64 Combinational Logic Design 16 CSE261 Spring 2008 Quine-McCluskey algorithm Quine1. Real-World Logic Design RealLots more than 6 inputs Design correctness more important than gate minimization Use Minimization process can be made into a program, using appropriate algorithms and data structures. guaranteed to find `minimal' solution minimal' 2. Required computation has exponential complexity (run time and storage) works well for functions with up to 8-12 variables, but 8quickly blows up for larger problems. `higher-level language' to specify logic operations higherlanguage' Use programs to manipulate logic expressions and minimize logic. PALASM, VHDL, VHDL, ABEL -- developed for PLDs 3. Heuristic programs (e.g., Espresso) used for larger problems, usually give minimal results. CSE261 Combinational Logic Design #65 #65 Verilog -- developed for ASICs CSE261 Combinational Logic Design #66 #66 ABEL Advanced Boolean Equation Language Developed for use with programmable logic devices, which have a programmable AND-OR structure. ANDCombinational logic functions Operators: Sets: ABEL Program Structure module module name title string device ID device deviceType; deviceType; pin declarations other declarations equations equations test_vectors test vectors end module name CSE261 Combinational Logic Design #68 #68 AND, OR, NOT, XOR, XNOR, & # ! $ !$ XBUS = [X3,X2,X1,X0]; XBUS = [1,1,0,1]; XBUS = 13; (XBUS == YBUS) Relations: Intermediate variables: (XBUS > [1,1,0,1]) CSE261 Combinational Logic Design #67 #67 Combinational Logic Design 17 CSE261 Spring 2008 ABEL Example Module Alarm_circuit Title `Alarm Circuit Example ALARMCKT device `P16V8C'; P16V8C' "Input pins PANIC, ENABLE, EXITING WINDOW, DOOR, GARAGE "Output pins ALARM "intermediate equation SECURE = WINDOW & DOOR & GARAGE; equations ALARM = PANIC # ENABLEA & !EXITING & !SECURE; CSE261 Combinational Logic Design #69 #69 ABEL Example (continued) test_vectors ([PANIC, ENABLEA,EXITING,WINDOW,DOOR,GARAGE] [ 1, 0, 0, 0, 0, 0, 0, .X., 0, 1, 1, 1, 1, 1, .X., .X., 1, 0, 0, 0, 0, .X., .X., .X., 0, .X., .X., 1, .X., .X., .X., .X., 0, .X., 1, .X.] .X.] .X.] .X.] .X.] 0] 1] [ [ [ [ [ [ [ [ALARM]) 1]; 0]; 0]; 1]; 1]; 1]; 0]; pin 1,2,3; pin 4,5,6; [ [ [ pin 11 istype `com'; com' [ [ [ End Alarm_Circuit CSE261 Combinational Logic Design #70 #70 ABEL language processor (compiler) 1. 2. 3. 4. ABEL equations file (cont.) Equations: ALARM = (ENABLE & !EXITING & !DOOR # ENABLEA & !EXITING & !WINDOW # ENABLEA & !EXITING & !GARAGE # PANIC); Reverse-Polarity Equations: Reverse!ALARM = (!PANIC & WINDOWS & DOOR & GARAGE # !PANIC & EXITING # !PANIC & !ENABLEA); Checks syntax Checks device-pin capabilities deviceExpands language statements and equations Reduces equations into sum-of-products form form for sum- ofprogrammable logic device (PLD) Checks test vectors against equations Checks equation requirements (# of inputs, product terms) against PLD resources Determines `fuse map' to program the PLD map' CSE261 Combinational Logic Design #71 #71 5. 6. 7. CSE261 Combinational Logic Design #72 #72 Combinational Logic Design 18 CSE261 Spring 2008 ABEL WHEN Statements Analysis WHEN (!A#B) THEN X1=C&!D; X1 = (!A#B)&(C&!D); WHEN (A&B) THEN X2=C#D; ELSE X2=E#F; X2=(A&B)&(C#D)#!(A&B)&(E#F); Logic Circuit Summary Logic Function Truth Table Truth Table Synthesis Logic Function Nested WHEN Statements WHEN (A) THEN X3=D; ELSE WHEN (B) THEN X3=E; ELSE WHEN (C) THEN X3=F; X3=(A)&(D) #!(A)&(AB)&(E) #!(A)&!(B)&(C)&(F); CSE261 Combinational Logic Design #73 #73 Canonical sum / Canonical product Boolean algebra theorems / K-Maps / Programs K- The minimal sum / product implementations CSE261 Combinational Logic Design #74 #74 Logic Circuit Next 1. Documentation Standards 2. Programmable Logic Devices 3. Decoders 4. Encoders 5. Three-state devices Three6. Multiplexers 7. XOR gates 8. Comparators 9. Adders 10. Comparators 11. Multipliers 12. Read-only memories (ROMs) ReadCSE261 Combinational Logic Design #75 #75 Combinational Logic Design 19 ...
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This note was uploaded on 05/08/2008 for the course CSE 261 taught by Professor Ercanli during the Spring '08 term at Syracuse.

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