Unformatted text preview: CSE261 April 2008 State Diagram Design
state table covers all input combinations and states Synchronous Design with State Machines state diagram has arcs with input combinations or transition equations More Often No graphical than state table design simpler, but error prone guarantee of all input combinations Possibly ambiguous  possibly no next state or more than one next state for some input combinations 1 State Machine Example 2 Example Tbird Tail Lights Example3 inputs  LEFT, RIGHT, HAZ
Layout of tail lights Example Tbird Tail Lights ExampleLeft Tail Light sequences Right LA RA RB RC LC LB Left = 4 states Right = 4 states HAZ = 2 states LC LB LA RA RB RC HAZ State Machine Example 3 State Machine Example 4 Sequential Circuit Example 1 CSE261 April 2008 Example First State Diagram ExampleMoore LEFT Example Output Table ExampleL2
1 1 State LC 0 0 0 1 0 0 0 1 LB 0 0 1 1 0 0 0 1 LA 0 1 1 1 0 0 0 1 RA 0 0 0 0 1 1 1 1 RB 0 0 0 0 0 1 1 1 RC 0 0 0 0 0 0 1 1 Machine design + RIGHT + HAZ starts sequence, continues unconditionally L3
PROBLEM L1
1
LEFT IDLE L1 L2  If multiple inputs TRUE? multiple next states! 1 need to be mutually exclusive and all inclusive
1 Transitions IDLE
HAZ RIGHT LR3 L3 R1 R2 R3 LR3 (LEFT + RIGHT + HAZ)' HAZ)' R3
1 1 R1 (LEFT' RIGHT' HAZ') (LEFT' RIGHT' HAZ' R2
State Machine Example
5 State Machine Example 6 Example Second State Diagram ExampleUnambiguous HAZ Example Third State Diagram Example(LEFT HAZ' RIGHT') HAZ' RIGHT' 1 L2
1 = highest priority HAZ interrupts L, R sequences quickly Ready to complete circuit L2
HAZ' HAZ' HAZ' HAZ' HAZ Operational PROBLEM: L, R cycle completes even if HAZ is asserted Dangerous L3
1 L1
1 LEFT HAZ' RIGHT' HAZ' RIGHT' L3
1 L1
1 IDLE
1 LR3
(HAZ + LEFT RIGHT) (LEFT + RIGHT + HAZ)' HAZ)' HAZ + LEFT RIGHT 1 IDLE LR3
HAZ R3
(LEFT + RIGHT + HAZ)' HAZ)' 1 1 R1
RIGHT HAZ' LEFT HAZ'
7 R3
HAZ' HAZ' R1
HAZ' HAZ' HAZ (RIGHT HAZ' LEFT') HAZ' LEFT' R2
State Machine Example R2
State Machine Example 8 Sequential Circuit Example 2 CSE261 April 2008 Example State Assignment Example Example Transition List ExampleAlternative to transition table for state diagram design method
S IDLE IDLE IDLE IDLE L1 L1 L2 L2 L3 R1 R1 R2 R2 R3 LR3 Q2 Q1 Q0 000 000 000 000 001 001 011 011 010 101 101 111 111 110 100 Transition Expr (LEFT+RIGHT+HAZ)' (LEFT+RIGHT+HAZ)' LEFT+HAZ'.RIGHT' LEFT+HAZ' .RIGHT' HAZ+LEFT.RIGHT RIGHT.HAZ'.LEFT' RIGHT.HAZ' .LEFT' HAZ' HAZ' HAZ' HAZ' HAZ' HAZ' HAZ 1 HAZ' HAZ' HAZ HAZ' HAZ' HAZ 1 1 S* IDLE L1 LR3 R1 L2 LR3 L3 LR3 IDLE R2 LR3 R3 LR3 IDLE IDLE Q2*Q1*Q0* 000 001 100 101 011 100 010 100 000 111 100 110 100 000 000
10 State Assignment: Assignment:
Initially Q2 Q1 all zeros determines Left vs. Right turn sequence One row per transition Q0 count graycode sequence to minimize graystate variable transitions Direct input to Max+2 state machine entry or manual synthesis State Machine Example 9 State Machine Example Example Next State and Output generation Example Example Output Table ExampleState 000 001 011 010 101 111 110 100 IDLE L1 L2 L3 R1 R2 R3 LR3 LC 0 0 0 1 0 0 0 1 LB 0 0 1 1 0 0 0 1 LA 0 1 1 1 0 0 0 1 RA 0 0 0 0 1 1 1 1 RB 0 0 0 0 0 1 1 1 RC 0 0 0 0 0 0 1 1 Q2* = Q2'.Q1'.Q0'.(HAZ+RIGHT) + Q2'.Q0.HAZ+Q2.Q0 Q2' .Q1' .Q0' Q2' Q1* = Q0.HAZ' Q0.HAZ' Q0* = Q2.Q1'.HAZ'.(LEFTRIGHT) + Q1'.Q0.HAZ' Q2.Q1' .HAZ' .(LEFT Q1' .Q0.HAZ' LA = Q2'.Q0 + Q2'.Q1 + Q2.Q1'.Q0' Q2' Q2' Q2.Q1' .Q0' LB = Q2'.Q1 + Q2.Q1'.Q0' Q2' Q2.Q1' .Q0' LC = Q2'.Q1.Q0' + Q2.Q1'.Q0' Q2' .Q1.Q0' Q2.Q1' .Q0'
State Machine Example
11 RA = Q2 RB = Q2.Q0' + Q2.Q1 Q2.Q0' RC = Q2.Q0' Q2.Q0'
12 State Machine Example Sequential Circuit Example 3 CSE261 April 2008 Example Circuit Block Diagram Example Example Circuit Diagram Example HAZARD RIGTH LEFT Q2* Q2 LC LB LA RA RB RC Q1* Q1 Q0* Q0 State Machine Example 13 State Machine Example 14 Sequential Circuit Example 4 ...
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 Spring '08
 Ercanli
 New Jersey, HAZ

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