L5 - Review ECS 154B Computer Architecture II Winter 2008 PC IorD PCSource ALUOp Control MemRead ALUSrcB MemWrite ALUSrcA MemtoReg RegWrite IRWrite

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ECS 154B Computer Architecture II Winter 2008 Multi-Cycle MIPS §5.5-5.6 Adapted from slides by Mary Jane Irwin, Penn State 2 Review Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr [31-26] 32 28 Control 3 Defining the CPU Control • Use a finite state machine model to understand and design the control • Signal names within each state (circle) are asserted during that cycle – Asserted signals are set or enabled – Unlisted signals are deasserted • Arcs between states list conditions for transition • Example State A – Signal Run asserted – Goes to State B when input Up = 0 – Goes to State C when input Up = 1 Run Up=1 Up=0 A B C 4 Instruction Fetch and Decode Cycles MemRead IorD = 0 IRWrite ALUSrcA = 0 ALUSrcB = 01 ALUOp = 00 PCSource = 00 PCWrite Instruction Fetch Start ALUSrcA = 0 ALUSrcB = 11 ALUOp = 00 Next state depends on instruction Decode MemRead IorD IRWrite Fetch Instruction
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This note was uploaded on 05/06/2008 for the course ECS 154b taught by Professor Krado during the Winter '08 term at UC Davis.

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L5 - Review ECS 154B Computer Architecture II Winter 2008 PC IorD PCSource ALUOp Control MemRead ALUSrcB MemWrite ALUSrcA MemtoReg RegWrite IRWrite

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