L6 - Registered Logic Blocks ECS 154B Computer Architecture...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
1 ECS 154B Computer Architecture II Winter 2008 Multi-Cycle MIPS Control Appendix C and §5.7 2 Registered Logic Blocks • What is a registered input or output? – Use registers to hold input or output – Needed in some cases – Causes problems when used unneeded Combinational Logic Combinational Logic Unregistered Registered 3 Unregistered Example • Clock Cycle 0 • Clock Cycle 1 • Clock Cycle 2 Combinational Logic 0x2D 0x2E Combinational Logic 0x34 0x35 Combinational Logic 0x79 0x7A 4 Registered Example • Clock Cycle 0 • Clock Cycle 1 • Clock Cycle 2 Combinational Logic 0x2D 0x2E 0x?? 0x34 Combinational Logic 0x34 0x35 0x2E 0x79 Combinational Logic 0x79 0x7A 0x35 0x??
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 5 Lab 1 Instruction Memory • What should be registered in Lab 1? Instruction Memory 6 Registered LPM_ROM 7 Unregistered LPM_ROM 8 Single Cycle Control • Very simple – Control signals are functions of opcode and possibly function fields – Combinational logic suffices • Ex: RegWrite – Asserted on R-type , lw – Deasserted on beq , sw , j
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 05/06/2008 for the course ECS 154b taught by Professor Krado during the Winter '08 term at UC Davis.

Page1 / 4

L6 - Registered Logic Blocks ECS 154B Computer Architecture...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online