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Unformatted text preview: ECS 154B Computer Architecture II Winter 2008 Pipelining Datapath and Control §6.2-6.3 Partially adapted from slides by Mary Jane Irwin, Penn State 2 Pipelined CPU • Break execution into five stages • Corresponds to the five instruction cycles – Fetch from instruction memory (IM) – Decode and fetch registers (Reg) – Execute the operation in the ALU – Access data memory (DM) – Write result back to register (Reg) A L U IM Reg DM Reg 3 State Registers • How do we store values across pipeline stages? – Multi-cycle MIPS introduced state registers – IR, MDR, B, A introduced – Sufficient for a pipelined CPU? Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUOut 4 Pipelined State Registers • Each instruction must maintain its own state • Any information needed by a later stage must be passed along • Consider PC + 4 – Computed during Fetch stage (why?) – Needed by Execute stage (why?) 5...
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- Winter '08
- Computer Architecture, Central processing unit, Instruction pipeline, Addr Write Data