This preview shows pages 1–3. Sign up to view the full content.
This preview has intentionally blurred sections. Sign up to view the full version.View Full Document
Unformatted text preview: 1 ECS 154B Computer Architecture II Winter 2008 Data Hazards §6.4 – 6.5 Adapted from slides by Mary Jane Irwin, Penn State 2 The Pipelined CPU So Far Read Address IM Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Shift left 2 DM Address Write Data Read Data IF/ID Sign Extend ID/EX EX/MEM MEM/WB ALU Cntrl RegWrite MemWrite MemRead MemtoReg RegDst ALUOp ALUSrc Branch PCSrc Control Add 3 Data Hazard Review • Caused when data is needed before it is ready – Read before write: Result of previous instruction needed by later instruction – Load use: Value in data memory needed by later instruction A L U IM Reg DM Reg A L U IM Reg DM Reg A L U IM Reg DM Reg 4 Read Before Write Hazard Solution • Stalling always an option • Forwarding data improves CPI over stalling A L U IM Reg DM Reg A L U IM Reg DM Reg A L U IM Reg DM Reg add $4, $5, $6 add $8, $4, $6 add $10, $9, $4 2 5 Data Forwarding • Take the result from the earliest point that it exists in any of the pipeline state registers and forward it to the functional units (e.g., the ALU) that need it that cycle • For ALU functional unit: the inputs can come from any pipeline register rather than just from ID/EX by...
View Full Document
This note was uploaded on 05/06/2008 for the course ECS 154b taught by Professor Krado during the Winter '08 term at UC Davis.
- Winter '08