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Unformatted text preview: 1 ECS 154B Computer Architecture II Winter 2008 Introduction to Pipelining §6.1 Partially adapted from slides by Mary Jane Irwin, Penn State 2 CPU Review • Single cycle CPU • Multi-cycle CPU State element State element Combinational logic clock one clock cycle or instruction State Element 1 Combinational logic State Element 2 … State Element N-1 Combinational logic State Element N clock one instruction … one clock cycle 3 Performance Review • Performance Equation: T = CPI • I • P = CPI • I / f • Multi-cycle CPU has high CPI, despite other advantages over single cycle • How can we improve CPI (throughput)? 4 Pipelining Increases Throughput • Use pipelining to increase throughput – Fetch next instruction before the current instruction has finished – Does not decrease instruction latency – Reuse resources across instructions • Alternatives – Superscalar: Execute multiple instructions in parallel – Break up elements to decrease clock cycle 2 5 Pipelining Example...
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This note was uploaded on 05/06/2008 for the course ECS 154b taught by Professor Krado during the Winter '08 term at UC Davis.
- Winter '08