L14 - Exceptions ECS 154B Computer Architecture II Winter...

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1 ECS 154B Computer Architecture II Winter 2008 Exceptions and Advanced Pipelining §6.8 – 6.9 Partially adapted from slides by Mary Jane Irwin, Penn State 2 Exceptions • Exceptions occur for several reasons – Invalid instruction – I/O device request – Undefined instruction – Hardware malfunction • CPU must catch the exception – Flush the pipeline before the instruction that caused the exception – Allow the pipeline after the instruction that caused the exception to complete – Record the cause and location of the exception 3 Exception Location • Exceptions may occur in several stages of the pipeline – Overflow: Execute stage – Cache Miss: Fetch or Memory stage – Invalid Instruction: Decode stage • Interrupts may occur at any time – Caused by external event – Not associated with an instruction or stage – CPU has some flexibility on when to handle • Several exceptions and interrupts may occur during the same clock cycle – Exceptions prioritized – CPU handles exception with highest priority 4 Flushing The Pipeline ALU IM Reg DM Reg add Overflow or sub and nor Address and Cause saved
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2 5 Flushing The Pipeline ALU IM Reg DM Reg nop Allow previous instruction to complete nop and nop Exception handling code 6 Flushing The Pipeline Flushes Instructions Saves Cause and Instruction Address 7 Advanced Pipelining • Pipelining improves performance by taking
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L14 - Exceptions ECS 154B Computer Architecture II Winter...

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