L7 - Single Microprogram ROM ECS 154B Computer Architecture...

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1 ECS 154B Computer Architecture II Winter 2008 Multi-Cycle MIPS Control Appendix C and §5.7 2 Single Microprogram ROM • ROM requires 20 kbits • Many entries are redundant – Decode cycle always follows fetch cycle • Addresses XXXXXX 0000 always contain same value • 2 6 -1 = 63 wasted entries – Some inputs invalid • Addresses 111111 XXXX indicate invalid instruction • 2 4 -1 = 15 wasted entries per bad opcode • Save space by dividing control into two ROMs – One ROM generates the next state – One ROM generates the control signals 3 Two Microprogram ROMs • Total ROM Size – 2 10 4 bit words for State ROM – 2 4 16 bit words for Control ROM – 4096 + 256 = 4352 ≈ 4.3 kbits Control Unit Microprogram State Instruction Control Signals Next State Control Signal ROM State ROM 4 Microprogram State ROM • The State ROM still wastes space – Most states increment to next value – Select source of next state in microinstruction • ROM Size 2 10 2 bit words = 2 kbits Control Unit Microprogram State Instruction Next State Selection Logic State ROM 1 + Next State Source Selection
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This note was uploaded on 05/06/2008 for the course ECS 154b taught by Professor Krado during the Winter '08 term at UC Davis.

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L7 - Single Microprogram ROM ECS 154B Computer Architecture...

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