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L1 - Course Overview ECS 154B Computer Architecture II...

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1 ECS 154B Computer Architecture II Winter 2008 Course Introduction MIPS Instructions (§2.1-2.9) Adapted from slides by Mary Jane Irwin, Penn State 2 Course Overview Instructor: Kurtis Kredo II TA: V S K Chaitanya Lecture: MWF 12:10-1:00 in Olson 223 Disc: M 2:10-3:00 in Art 217 (Attend!) Text: Patterson and Hennessy Computer Organization and Design, 3 rd Edition Required Text – Needed to complete labs and homework Website: http://wwwcsif.cs.ucdavis.edu/~cs154b/ 3 Course Overview: Communication • Kurtis Email: [email protected] (ECS 154B in subject) – Office: Kemper 3052 OH: T/Th 1:00-2:00 and W 11:00-12:00 – Phone: 754-9587 (Only during office hours) • Chaitanya – Email: cs154b @cs.ucdavis.edu – Office: Kemper 53 OH: Friday 4:00-6:00 • Newsgroups ucd.class.ecs154b for Announcements (Read only) – ucd.class.ecs154b.d for Student Discussions 4 Course Overview: Grading • Homework – Not collected or graded – Still do the homework Helps you study for exams Helps you master the material – Four over the quarter from text – Individual work Midterm (25%) – February 13 Final (35%) – March 18 at 1:00
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2 5 Course Overview: Grading Labs (40%) – Four over the quarter – Groups of two or three students – 10% per day late penalty – Short (1-2 pages) lab report required – Grading done interactively in TA office – See lab guidelines and lab handout for submission procedure and more info 6 Course Overview: Schedule Multiprocessors (9) 10 I/O (8) and Multiprocessors (9) 9 Caches and Virtual Memory (7) 8 Caches (7) 7 Performance, Midterm, and History 6 Pipelining (6) 5 Pipelining (6) 4 Processor (C), Performance (4) 3 Processor (5) 2 MIPS Instructions (2) and Processor (5) 1 Topic Week A more detailed schedule is on the course website. 7 Computer Organization Processor (CPU) Control and Datapath Perform computation Memory Primary (RAM, cache) Stores instructions and data for programs Input / Output Peripheral devices Disks, networks, mouse, display We will study all five areas of the computer Processor (Ch. 5 & 6) Memory (Ch. 7) I/O (Ch. 8) 8 Instruction Set Architecture The instruction set defines what operations the processor can do – “Language” of the computer – Processor executes instructions to perform task Instructions stored in memory like data The stored-program concept – Two architectures von Neumann: data and instructions in same space Harvard: data and instructions in separate spaces
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3 9 MIPS Instruction Set Architecture (ISA) Instruction Categories – Computational – Load/Store Jump and Branch Floating Point coprocessor Memory Management – Special R0 - R31 PC HI LO Registers opcode 3 Instruction Formats: all 32 bits wide R format I format J format rs rt rd shamt funct opcode rs rt immediate opcode address 11
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