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L10 - CPU Pipelining Example ECS 154B Computer Architecture...

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1 ECS 154B Computer Architecture II Winter 2008 Introduction to Pipelining §6.1 Partially adapted from slides by Mary Jane Irwin, Penn State 2 CPU Pipelining Example ALU IM Reg DM Reg ALU IM Reg DM Reg ALU IM Reg DM Reg ALU IM Reg DM Reg Instruction A Instruction B Instruction C Instruction D One Clock Cycle 3 Pipelining Difficulties Pipelining introduces some difficulties Hazards must be resolved – Structural Hazard Conflict caused by CPU architecture Using the same resource at the same time – Data Hazard Conflict caused by instruction order Using a register value before it is computed – Control Hazard Conflict caused by not knowing next instructions Instructions to execute after conditional branches 4 Data Hazards Read before write data hazard ALU IM Reg DM Reg ALU IM Reg DM Reg ALU IM Reg DM Reg ALU IM Reg DM Reg add $1, $4, $5 add $8, $9, $1 add $7, $12, $1 add $2, $3, $1
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2 5 Fixing Data Hazards Could fix with stalls ALU IM Reg DM Reg ALU IM Reg DM Reg add $1, $4, $5
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