L15 - Pipelined CPU ECS 154B Computer Architecture II...

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1 ECS 154B Computer Architecture II Winter 2008 Pipelined Performance Pipelined CPU • A pipeline increases performance by increasing throughput for the CPU – CPI decreases from multi-cycle – Clock cycle decreases from single cycle • Each instruction takes 5 cycles, the pipeline has 5 stages, so the CPI equals 1! Right? • We divide the instruction into 5 cycles, so the new clock cycle is one fifth the old cycle! Right? • For an n stage pipeline we get a factor of n in performance improvement! Right? Pipelined CPU Limitations • Pipeline performance limited by several factors: – Hazards • Branch stalls/misprediction • Load-use stalls – State register overhead • It takes time to write the state registers • Clock cycle must be lengthened to account for this – Pipeline divided unequally • Some stages take longer than others • Clock cycle limited by slowest stage Pipelined Example • A workload has the following instruction mix: • With a 200 ps clock cycle and 10,000 instructions, what is the performance? • Average CPI:
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L15 - Pipelined CPU ECS 154B Computer Architecture II...

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