L18 - Handling Cache Hits ECS 154B Computer Architecture II...

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1 ECS 154B Computer Architecture II Winter 2008 Caches 7.2 Adapted from slides by Mary Jane Irwin, Penn State 2 Handling Cache Hits • Read hits (Instruction or Data Memory) – This is what we want! • Write hits (Data Memory) – Allow cache and memory to be inconsistent • Write the data only into the cache block Write back the cache contents to the next level in the memory hierarchy when that cache block is “evicted” • Need a dirty bit for each data cache block to tell if it needs to be written back to memory when it is evicted – Require the cache and memory to be consistent • Always write the data into both the cache block and the next level in the memory hierarchy ( write-through ) so don’t need a dirty bit • Writes run at the speed of the next level in the memory hierarchy • Can use a write buffer , so only have to stall if the write buffer is full 3 Write Buffer for Write-Through Caching • Write buffer between the cache and main memory – Processor: writes data into the cache and the write buffer – Memory controller: writes contents of the write buffer to memory • The write buffer is just a FIFO – Typical number of entries: 4 – Works fine if store frequency << 1 / DRAM write cycle • Memory system designer’s nightmare – When the store frequency → 1 / DRAM write cycle leading to write buffer
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This note was uploaded on 05/06/2008 for the course ECS 154b taught by Professor Krado during the Winter '08 term at UC Davis.

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L18 - Handling Cache Hits ECS 154B Computer Architecture II...

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