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Unformatted text preview: 1 ECS 154B Computer Architecture II Winter 2008 Multi-Cycle MIPS 5.5 Adapted from slides by Mary Jane Irwin, Penn State 2 Reasons for Multi-cycle Operation Single cycle CPU wasteful Clock period must accommodate slowest instruction Multiple functional units (memory, adders) Multiple cycle CPU better Clock period is determined by longest operation Functional units can be shared Reduces chip area However, only one use per clock cycle Instructions can take a different number of clock cycles to complete Prepares you for introduction of pipelining 3 Multi-cycle Approach Let instructions take more than one clock cycle Break instruction into steps that occur in one cycle Balance steps to minimize clock period Each resource used only once per step Not all instructions need every step Reuse resources to save chip area ALU used to calculate PC+4 and branch offset in addition to instruction operation Single memory for instructions and data 4 Multi-cycle Approach Single cycle CPU Multi-cycle CPU Requires state elements to hold intermediate values State element State element Combinational logic clock one clock cycle or instruction State Element A Combinational logic State Element B State Element N-1 Combinational logic State Element N clock one instruction one clock cycle 2 5 Multi-cycle Approach Each cycle must Store values needed in a later cycle of the current instruction in an internal register. All except IR hold data for one clock cycle....
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- Winter '08