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Unformatted text preview: ECS 154B Lab 1 Winter 2008 ECS 154B – Winter 2008 – Lab 1 Due by 11:59 January 21 Objectives • Build and test a single cycle MIPS CPU that implements a subset of the MIPS instruction set • Design a combinational logic control unit Description In this lab you will use Quartus to build a single cycle CPU to understand the MIPS control and datapath signals. To test your CPU, you will run assembly language programs that you write on it and simulate the operation in Quartus. You will be given several functional blocks to help you out and an assembler that will generate a file to initialize your program memory. You may find figures 5.12 and 5.17 from your text helpful. You must implement the control signals as combinational logic. During interactive grading you will be given an initialization file to run that will use all the required instructions. Details It is important for this lab that you select “APEX II” as the device family when creating your project and logical blocks. If you forget to select APEX II when you create your project, you can change it by selecting Assignments → Device. Any generated logical blocks must also use the APEX II device family. You can safely ignore the message that APEX II is not a recommended family. When generating your instruction memory, make it a word addressable memory with a depth of 128. Thus, no program may be longer than 128 instructions. Use lab1.mif as your instruction memory initialization file name....
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- Winter '08
- Central processing unit, MIPS architecture, Register file, 32-bit data