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Unformatted text preview: ECS 154B Lab 2 — Due 11:59 February 6 Winter 2008 Lab 2 Due 11:59 February 3 Due 11:59 February 6 Objectives • Build and test a multi-cycle MIPS CPU that implements a subset of the MIPS instruction set • Design a microcode control unit Description In this lab you will use Quartus to build a multi-cycle CPU to understand the MIPS control and datapath signals. To test your CPU, you will run assembly language programs that you write and simulate the operation in Quartus. You will be given an ALU to help you out and an assembler that will generate a file to initialize your memory. You may find Figure 5.28 and the figures in Appendix C from your text helpful. You must implement the CPU control using microcode as discussed in class. During interactive grading you will be given an initialization file to run that will use all the required instructions. Details It is important for this lab that you select ”APEX II” as the device family when creating your project and logical blocks. If you forget to select APEX II when you create your project, you can change it by selecting Assignments → Device. Any generated logical blocks must also use the APEX II device family. You can safely ignore the message that APEX II is not a recommended family. Your program counter (PC) must be 32 bits and it must address bytes. Any other choice will result in a loss of points. When generating your memory, make it 128 words deep. Logically (not in your design) reserve the first 64 words for instructions and the last 64 words for data....
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This note was uploaded on 05/06/2008 for the course ECS 154b taught by Professor Krado during the Winter '08 term at UC Davis.
- Winter '08