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Unformatted text preview: ECS 154B Lab 3 — Due 11:59 February 26 Winter 2008 Lab 3 Due by 11:59 February 26 Objectives • Build and test a pipelined MIPS CPU that implements a subset of the MIPS instruction set • Handle data and control hazards through stalling and forwarding Description In this lab you will use Quartus to build a pipelined CPU to understand the MIPS architecture. To test your CPU, you will run assembly language programs that you write and simulate the operation in Quartus. You will be given an ALU to help you out and an assembler that will generate a file to initialize your instruction memory. You may implement the CPU control in any way you choose. You must support forwarding and hazard detection as outlined later in the lab description. During interactive grading you will be given an initialization file to run that will use all the required instructions. Details It is important for this lab that you select ”APEX II” as the device family when creating your project and logical blocks. If you forget to select APEX II when you create your project, you can change it by selecting Assignments → Device. Any generated logical blocks must also use the APEX II device family. You can safely ignore the message that APEX II is not a recommended family. Your program counter (PC) must be 32 bits and it must address bytes. Any other choice will result in a loss of points. When generating your instruction memory, make its depth 128 words. You will be given an ALU (available on the course website) to start your lab. This is the same ALU from Lab 2 and you must use this ALU. Simply download the tar file, extract the files into your project directory, and insert the ALU like any other logic block. The ALU will be listed under the Project folder in the Insert Symbol dialog box.Symbol dialog box....
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- Winter '08
- Central processing unit, MIPS architecture