Lab4 - ECS 154B Lab 4 Due 11:59 March 17 Winter 2008 Lab 4...

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Unformatted text preview: ECS 154B Lab 4 Due 11:59 March 17 Winter 2008 Lab 4 Due 11:59 March 17 Objectives Investigate the optimal cache configuration for several program memory address listings Examine the effect of large block size on conflict and capacity misses Explore the use of FIFO block replacement as an approximation to LRU Description In this lab you will use build a cache simulator in C or C++ to study caches and how cache structure affects program performance. You will use memory address listings from three real programs to determine the optimal cache organization for each program. Use total time, hit time plus any miss penalty, as your evaluation metric, so the optimal organization is the one with the lowest total time. Using the results of your simulation, you will describe the memory access patterns for the programs and answer several questions. Details Your cache simulator will read addresses from a file and measure the performance of the cache as the program runs in simulation. The simulator must have a specific input and output. The simulator arguments are defined as follows: cachesim <BlockSize> <SetCount> <Associativity> <ReplacementAlg> <TraceFile> where Parameter Type Meaning cachesim Your program must be called cachesim . BlockSize Integer The block size for the cache in words . You can assume this is a power of 2. SetCount Integer The number of sets in the cache (e.g., 1 for fully associative, the number of blocks for direct mapped). You can assume this is a power of 2. Associativity Integer The cache associativity (e.g., 1 for direct mapped, 2 for two-way sets). You can assume this is a power of 2. ReplacementAlg Character The block replacement algorithm to use. f selects FIFO replace- ment and l selects LRU replacement. Thats a lower case F or a lower case L. TraceFile String The filename of the trace file to use for simulation. You may use additional parameters to your simulator after the required parameters, such as debug flags, but your simulator must work with the above parameters. Your simulator must track the number of hits and misses in the cache caused by the memory accesses. Additionally, you must classify and track the misses as either compulsory, conflict, or capacity misses. As you learned in lecture, a high hit rate or low miss rate ECS 154B Lab 4 Due 11:59 March 17 Winter 2008 is not the only goal, so you must also compute the total time spent accessing memory for the simulated program. Your simulator should output three lines of results with the number of hits, the number of misses and their classification, and the total time, each on a separate line and in that order. When reporting the miss classification, report them in the form (Compulsory/Conflict/Capacity) unless you provide additional output. The hit and miss counts must be reported as integer values and the total time must be reported as a floating point value expressed in seconds . An example output appears below....
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This note was uploaded on 05/06/2008 for the course ECS 154b taught by Professor Krado during the Winter '08 term at UC Davis.

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Lab4 - ECS 154B Lab 4 Due 11:59 March 17 Winter 2008 Lab 4...

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