L23 - Bus Basics ECS 154B Computer Architecture II Winter...

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1 ECS 154B Computer Architecture II Winter 2008 Buses and I/O 8.4-8.7 Adapted from slides by Mary Jane Irwin, Penn State 2 Bus Basics • A bus is a shared communication link (a single set of wires used to connect multiple subsystems) that needs to support a range of devices with widely varying latencies and data transfer rates – Advantages • Versatile – new devices can be added easily and can be moved between computer systems that use the same bus standard • Low cost – a single set of wires is shared in multiple ways – Disadvantages • Creates a communication bottleneck – bus bandwidth limits the maximum I/O throughput • The maximum bus speed is largely limited by – The length of the bus – The number of devices on the bus 3 Bus Basics Control lines – Signal requests and acknowledgments – Indicate what type of information is on the data lines Data lines – Data, addresses, and complex commands • Bus transaction consists of – Master issuing the command (and address) – request – Slave receiving (or sending) the data – action – Defined by what the transaction does to memory • Input – inputs data from the I/O device to the memory • Output – outputs data from the memory to the I/O device Bus Master Bus Slave Control lines : Master initiates requests Data lines : Data can go either way 4 Bus Types • Processor-memory bus (proprietary) – Short and high speed – Matched to the memory system to maximize the memory- processor bandwidth – Optimized for cache block transfers • I/O bus (industry standard, e.g., SCSI, USB, Firewire) – Usually is lengthy and slower – Needs to accommodate a wide range of I/O devices – Connects to the processor-memory bus or backplane bus • Backplane bus (industry standard, e.g., ATA, PCIExpress) – The backplane is an interconnection structure within the chassis – Used as an intermediary bus connecting I/O busses to the processor-memory bus
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2 5 Bus Timing • Synchronous bus (e.g., processor-memory buses) – Includes a clock in the control lines and has a fixed protocol for communication that is relative to the clock – Advantage: involves very little logic and can run very fast – Disadvantages: • Every device communicating on the bus must use same clock rate • To avoid clock skew, wires cannot be long if they run fast • Asynchronous bus (e.g., I/O buses) – It is not clocked, so requires a handshaking protocol and additional control lines (ReadReq, Ack, DataRdy) – Advantages: • Can accommodate a wide range of devices and device speeds • Can be lengthened without worrying about clock skew or synchronization problems – Disadvantage: slow(er) 6 Asynchronous Bus Handshaking Protocol Output (read) data from memory to an I/O device I/O device signals a request by raising ReadReq and putting the address on the data lines 1. Memory sees ReadReq, reads address from data lines, and raises Ack 2. I/O device sees Ack and releases the ReadReq and data lines
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This note was uploaded on 05/06/2008 for the course ECS 154b taught by Professor Krado during the Winter '08 term at UC Davis.

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L23 - Bus Basics ECS 154B Computer Architecture II Winter...

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