L25 - 1 ECS 154B Computer Architecture II Winter 2008 Bus...

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Unformatted text preview: 1 ECS 154B Computer Architecture II Winter 2008 Bus Multiprocessors 9.3-9.4 Adapted from slides by Mary Jane Irwin, Penn State 2 Additional Reference Some information and more details provided in Parallel Computer Architecture by David Culler, Jaswinder Pal Singh, and Anoop Gupta Sections 5.3, 5.5, 6.3 Available in library reserves 3 Bus Multiprocessors A single bus used by all processors One memory for all processors Caches used to reduce latency and to lower bus traffic Must provide hardware for cache coherency and process synchronization Processor Processor Processor Cache Cache Cache Single Bus Memory I/O 4 Cache Coherency Through Snooping Bus snooping uses a cache controller to monitor shared bus traffic (reads and writes) Duplicate address tag hardware so as not to interfere with processors access to the cache Each cache block in one of several states Processor Bus Memory I/O Snoop Cache Processor Snoop Cache Processor Snoop Cache 2 5 Bus Snooping Protocols Multiple copies are not a problem when reading Processor must have exclusive access to write Multiple writing processors would break coherence Must get exclusive copy before a write Must notify other caches after a write Bus ensures all processors have the same state Bus broadcasts all reads/writes to all processors Bus does not allow simultaneous operations Only one processor per bus transaction...
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This note was uploaded on 05/06/2008 for the course ECS 154b taught by Professor Krado during the Winter '08 term at UC Davis.

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L25 - 1 ECS 154B Computer Architecture II Winter 2008 Bus...

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