L3 - 1 ECS 154B Computer Architecture II Winter 2008...

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Unformatted text preview: 1 ECS 154B Computer Architecture II Winter 2008 Single-Cycle MIPS 5.4 Adapted from slides by Mary Jane Irwin, Penn State 2 Our implementation of the MIPS is simplified Memory-reference instructions: lw , sw Arithmetic/Logical instructions: add , sub , and , or , slt Control flow instructions: beq , j Generic implementation Use the program counter (PC) to supply the instruction address and fetch the instruction from memory (and update the PC) Decode the instruction (and read registers) Execute the instruction All instructions (except j ) use the ALU The Processor: Datapath & Control Fetch PC = PC+4 Decode Exec 3 The Complete Datapath MemtoReg Read Address Instruction Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU zero ALUControl RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 16 32 ALUSrc PCSrc Add Shift left 2 4 Adding the Control Selecting the operations to perform (ALU, Register File and Memory read/write) Controlling the flow of data (multiplexer inputs) Observations op field always in bits 31-26 Address of registers to be read are always specified by the rs field (bits 25-21) and rt field (bits 20-16)...
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L3 - 1 ECS 154B Computer Architecture II Winter 2008...

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