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Unformatted text preview: 1. (1pts) What is the Hamming distance between these two bit patterns: 1101 and 0100? 2. (3pts) How far apart must valid code words be to allow Single Error Detection (SED)? Quadruple Error Correction (QEC)? Quintuple (5) Error Correction Sextuple (6) Error Detection (QECSED)? 3. (3pts) Write the equation for the carry out of the 4th adder cell in an ALU using carrylookahead, in terms of P's and G's. 4. (3pts) What is the difference between the Mealy and Moore models of sequential design? 5. (3pts) What is the difference between Sequential and Combinational Logic? 6. (2pts) What is a Karnaugh Map? 7. (6pts) We know that a single cell of a ripple carry adder implements the functions Cout = AB+ACin +BCin and Sum = A xor B xor Cin Assuming you have made a 4bit ripple carry adder using these cells, what is the worst case path through the adder? In other words, how long does it take for the answer to be correct in all cases? (I suggest you draw the circuit in order to make doing this problem easier). Use the following delay values, and assume all input signals become valid at time 0: 2input AND: 6 ns 3input AND: 8 ns 2input OR: 3input OR: 5 ns 6 ns 2input XOR: 9 ns 3input XOR: 12 ns 8. (9 pts) Assume you have 8bit data words, and your memory system supports Single Error Correction. For each of the following patterns recieved from memory identify and correct any errors that may have occurred during transmission or storage. Assume the same organization of carry and data bits as we used in class. The first one is done for you. Given: 0 0 1 0 1 1 0 1 0 1 1 1 Given: 0 0 1 1 1 0 0 1 1 0 0 0 The Data Word is: 00101011 The Data Word is: 9. (10 pts) You have derived the following karnaugh maps for the inputs to a JK flipflop. Unfortunately, the parts department just called and your company is completely out of JK flipflops. All they have left in stock is Toggle flipflops, which you will have to use instead. Show the resulting karnaugh map for the modified version of the circuit (the one that uses the Toggle instead of the JK flipflop.) J'
X K'
X 1 d d Y2 1 1 d d d d d 1 d Y3 d Y2 d d 1 d d 1 d d Y1 d 1 d Y1 D'
X Y3 Y2 Y1 Y3 10. (20pts) Given the following table, draw the Karnaugh maps for Y1', Y2', and Y3' and Z in terms of X, Y1, Y2 and Y3, and then write minimum boolean equations for each. Present State (Y1 Y2 Y3) 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 X=0 (Y1' Y2' Y3') 0 1 1 1 0 0 0 1 0 0 0 0 0 0 1 1 1 0 1 0 1 Next State X=1 (Y1' Y2' Y3') 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 Output (Z) X=0 X=1 1 0 1 1 1 0 0 1 0 1 0 0 0 1 Y2 Y2 Y1 Y1 X X Y3 Y3 Y2 Y2 Y1 Y1 X X Y3 Y3 Y2 Y2 Y1 Y1 X X Y3 Y3 11. (20 pts) Given the following Karnaugh maps, implement the sequential machine using an RS FF for Y1, a JK FF for Y2, and a Toggle FF for Y3. You do not need to draw the gates, but you do need to write down minimized input equations for each of the inputs of each of the Flip Flops in the circuit. Y1' 1 1 Y2 1 1 d 1 1 1 X 1 d 1 Y3 Y2' d 1 Y2 1 d 1 1 1 d 1 X 1 1 Y3' 1 Y3 Y2 1 Y1 1 1 1 1 X 1 Y3 1 Y1 Y1 X X X Y3 Y2 Y2 Y3 Y2 Y3 Y1 Y1 Y1 X X X Y3 Y2 Y2 Y3 Y2 Y3 Y1 Y1 Y1 12. (20 pts) Freedonia now wants a fancy new electronic lock for their treasury. The lock has two buttons, and the combination should be Left Right Right Left. Only one button can be pressed at a time. Let X1=Left Button and X2=Right Button. Z=1 indicates the lock should be opened, Z=0 signals lock closed. Draw the State Transistion Diagram (the circles and the arcs) for this finite state machine. Let S0=no buttons pressed (the Start state). Once you have a state transition diagram, minimize the number of states necessary and then assign bit patterns to each state and write down the corresponding state transition table. Assume you are using a Mealy model. Label the transitions on the diagram using the following format: X1 X2 Z So, for example, 01 0 would be used to indicate that the Right Button was pressed, and the output at that point should be a 0 (lock closed). ...
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This note was uploaded on 05/06/2008 for the course ECS 154a taught by Professor Singh during the Winter '05 term at UC Davis.
 Winter '05
 Singh

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