L17 - The Memory Hierarchy ECS 154B Computer Architecture...

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1 ECS 154B Computer Architecture II Winter 2008 Caches 7.1 – 7.2 Adapted from slides by Mary Jane Irwin, Penn State 2 The Memory Hierarchy • Take advantage of locality to present the user with as much memory as is available in the cheapest technology at the speed offered by the fastest technology Increasing distance from the processor increases access time L1$ L2$ Main Memory Secondary Memory Processor (Relative) size of the memory at each level Inclusive what is in L1$ is a subset of what is in L2$ is a subset of what is in MM is a subset of what is in SM 4-8 bytes ( word ) 1 to 4 blocks 1,024+ bytes ( disk sector = page ) 8-32 bytes ( block ) 3 A Typical Memory Hierarchy • By taking advantage of the principle of locality – Can present the user with as much memory as is available in the cheapest technology – at the speed offered by the fastest technology Second Level Cache (SRAM) Control Datapath Secondary Memory (Disk) On-Chip Components RegFile Main Memory (DRAM) Data Cache Instr ITLB DTLB Speed (cycles): ½’s 1’s 10’s 100’s 1,000’s Size (bytes): 100’s K’s 10K’s M’s G’s to T’s Cost: highest lowest 4 The Memory Hierarchy:
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This note was uploaded on 05/06/2008 for the course ECS 154b taught by Professor Krado during the Winter '08 term at UC Davis.

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L17 - The Memory Hierarchy ECS 154B Computer Architecture...

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