L2 - The Processor: Datapath & Control ECS 154B...

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1 ECS 154B Computer Architecture II Spring 2007 Single-Cycle MIPS §5.1, 5.3 Adapted from slides by Mary Jane Irwin, Penn State 2 • Our implementation of the MIPS is simplified – Memory-reference instructions: lw , sw – Arithmetic/Logical instructions: add , sub , and , or , slt – Control flow instructions: beq , j • Generic implementation – Use the program counter (PC) to supply the instruction address and fetch the instruction from memory (and update the PC) – Decode the instruction (and read registers) – Execute the instruction • All instructions (except j ) use the ALU The Processor: Fetch PC = PC+4 Decode Exec 3 Basic Elements • Functional units – Adders – Memories – ALU – Program counter • Logical units – Sign extension – Bit shifters – Multiplexers Add ROM ALU Sign Extend Shift left 2 PC 4 The Processor: Overview Read Address Instruction Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Data Memory Address Write Data Read Data Add
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2 5 Fetching Instructions • Fetching instructions involves – Reading the instruction from the Instruction Memory – Updating the PC to hold the address of the next instruction
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This note was uploaded on 05/06/2008 for the course ECS 154b taught by Professor Krado during the Winter '08 term at UC Davis.

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L2 - The Processor: Datapath & Control ECS 154B...

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