Class15 - EECE438/EECE570 SYSTEM ON A CHIP DESIGN Introduction to VHDL Exercise#4 Making use of the previous examples write an entity/architecture

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EECE438/EECE570 SYSTEM ON A CHIP DESIGN Introduction to VHDL
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Exercise #4 ± Making use of the previous examples, write an entity/architecture pair for the following design: ENR DIN Q REGISTER 4 4 Q P P=Q COMPARATOR 4 COUNT CLOCK ENC LD DATA ENR RESET (sync) ENC LD DIN Q COUNTER RST
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Exercise #4: Solution LIBRARY ieee; USE ieee.std_logic_1164 .ALL; USE ieee.std_logic_arith .ALL ; ENTITY ex4 IS PORT ( clock, reset, enc, enr, ld: IN std_logic; data: IN std_logic_vector (3 DOWNTO 0); count: BUFFER std_logic_vector(3 DOWNTO 0)); END ex4; ARCHITECTURE archex4 OF ex4 IS SIGNAL comp: std_logic; SIGNAL regout: std_logic_vector (3 DOWNTO 0); BEGIN reg: PROCESS (clock) BEGIN IF RISING_EDGE (clock) THEN IF enr = '1' THEN regout <= data; END IF ; END IF ; END PROCESS reg;
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Exercise #4: Solution (contd.) cntr: PROCESS (clock) BEGIN IF RISING_EDGE (clock) THEN IF reset = '1' THEN count <= "0000"; ELSIF ld = '1' THEN count <= data; ELSIF enc = '1' AND comp = '0' THEN count <= count + 1; END IF ; END IF ; END PROCESS cntr; comp <= '1' WHEN regout = count ELSE '0'; END archex4; Three concurrent blocks: two sequential statement + one concurrent statement Three concurrent blocks: Three concurrent blocks: two sequential statement + one concurrent statement two sequential statement + one concurrent statement
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State machines ± Moore Machines ± A finite state machine in which the outputs change due to a change of state ± Mealy Machines ± A finite state machine in which the outputs can change asynchronously i.e., an input can cause an output to change immediately
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Moore machines ± Outputs may change only with a change of state ± Multiple implementations include: ± Arbitrary state assignment ± outputs must be decoded from the state bits ± Specific state assignment ± outputs may be encoded within the state bits ± one-hot encoding
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Example: A Traffic Light Controller ± Let’s take a look at an example state machine and see how to describe it using different implementations: RESET (asynchronous) RED TIMER1 YELLOW GREEN TIMER1 TIMER2 TIMER2 Y='1' G='1' TIMER3 TIMER3 R='1'
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Example: The Entity Declaration ± The entity declaration remains exactly the same for each implementation. ± For example: LIBRARY ieee; USE ieee.std_logic_1164. ALL ; ENTITY state_machine IS PORT ( clock, reset: IN std_logic; timer1, timer2, timer3: IN std_logic; r, y, g: OUT std_logic); END state_machine;
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Example: Solution 1 ± Combinatorial outputs decoded from the state registers ARCHITECTURE arch_1 OF state_machine IS TYPE traffic_states IS (red, yellow, green); -- enumerated type SIGNAL sm: traffic_states; BEGIN fsm: PROCESS (clock, reset) -- the process describes the BEGIN -- state machine only IF reset = '1' THEN sm <= red; ELSIF rising_edge(clock) THEN CASE sm IS WHEN red => IF timer1=‘1’ THEN sm <= green; ELSE sm <= red; END IF ; WHEN green => IF timer2=’1' THEN sm <= yellow; ELSE sm <= green; END IF ;
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This note was uploaded on 05/08/2008 for the course EECE 438 taught by Professor Chen during the Spring '08 term at Binghamton University.

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Class15 - EECE438/EECE570 SYSTEM ON A CHIP DESIGN Introduction to VHDL Exercise#4 Making use of the previous examples write an entity/architecture

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