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class12 - EECE438/EECE570 SYSTEM ON A CHIP DESIGN...

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EECE438/EECE570 SYSTEM ON A CHIP DESIGN CoreConnect Bus Architecture
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PowerPC 405 5-stage data path pipeline 16KB D and I Caches Embedded Memory Management Unit Execution Unit – Multiply / divide unit – 32 x 32-bit GPR Dedicated on-chip memory interfaces Timers: PIT, FIT, Watchdog Debug and trace support Performance: – 450 DMIPS at 300 MHz – 0.9mW/MHz Typical Power
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CoreConnect™ Bus Architecture Device Control Register Bus (DCR) 32-bit bus for initiating peripherals Access status and control registers of PLB and OPB masters and slaves Saves PLB and OPB bandwidth Processor Local Bus (PLB) 32-bit address, 64-bit data Primary high-bandwidth bus interfacing “directly” with the processor On-chip Peripheral Bus (OPB) 32-bit address, 32-bit data Lower bandwidth bus interfacing to system peripherals Adopted from xilinx
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CoreConnect Example
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CoreConnect Based System
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CoreConnect Details Provides three buses for interconnecting cores, library macros, and custom logic: – Processor Local Bus (PLB) – On-Chip Peripheral Bus (OPB) – Device Control Register (DCR) Bus IBM offers a no-fee, royalty-free CoreConnect architectural license – Licensees receive the PLB arbiter, OPB arbiter and PLB/OPB bridge designs along with bus model toolkits and bus functional compilers for the PLB, OPB and DCR buses
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Processor Local Bus (PLB) High performance, synchronous on chip bus – 32-bit address, 64-bit write and 64-bit read data bus – Instruction Cache Unit PLB master is read only! Read/write transfers between master and slave devices Each PLB master has separate address, read data, write data, and transfer qualifiers PLB slaves have shared, but decoupled, address, read data, write data, transfer qualifiers, and status signals Access granted through a central arbitration mechanism
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PLB Block Diagram Slave and master do not talk with each other. Any information exchange is relayed through the bus arbiter. Slave and master do not talk with each other. Any information ex change is relayed through the bus arbiter. When multiple master requests are asserted, the arbiter grant th e bus to the one with the highest priority. e bus to the one with the highest priority. many many to to one one A write transaction A write transaction A write transaction moves data from moves data from master to slave while master to slave while a read transaction a read transaction moves data from moves data from slave to master. slave to master.
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PLB Features Architecture supports 8 PLB masters – Instruction Cache and Data Cache are PLB masters Timing is provided by a single, shared clock source Overlap read & write transfers permits 2 transfers/clock Piplelined transfer overlaps memory access delay Four levels of request priority for each master Byte enables for unaligned halfword and 3-byte transfers Support for 16-, 32- and 64-bit line data transfers Variable or fixed length burst transfers supported
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PLB Transfer Protocol: Address Cycles
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