class14 - EECE438/EECE570 SYSTEM ON A CHIP DESIGN...

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EECE438/EECE570 SYSTEM ON A CHIP DESIGN Introduction to VHDL
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Review PLB bus Waveform of read/write transfer Burst transfer Terminated by slave/master Fixed length burst Pipelined access Primary/secondary request Pipelined address phase and data phase
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ENTITY entity_name IS -- optional generics PORT ( name : mode type ; ... ) ; END entity_name ; entity_name is an arbitrary name generics are used for defining parameterized components name is the signal/port identifier and may be a comma separated list for ports of identical modes and types mode describes the direction the data is flowing type indicates the set of values name may be assigned The Entity Declaration
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Ports The Entity (“BLACK BOX”) has PORTS PORTS are the points of communication PORTS are usually the device pins PORTS have an associated name , mode , and type
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Port Modes A port’s MODE indicates the direction that data is transferred: IN Data goes into the entity only OUT Data goes out of the entity only (and is not used internally) INOUT Data is bi-directional (goes into and out of the entity) BUFFER Data that goes out of the entity and is also fed-back internally Entity
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Example: Generic Adder entity entity add_g add_g is is generic(left generic(left : natural := 31; : natural := 31; -- -- top bit top bit prop : time := 100 ps ps ); port (a : in port (a : in std_logic_vector std_logic_vector (left (left downto downto 0); 0); b : in : in std_logic_vector std_logic_vector (left (left downto downto 0); 0); cin cin : in : in std_logic std_logic ; sum : out std_logic_vector (left downto downto 0); cout cout : out : out std_logic std_logic ); ); end entity end entity add_g add_g ;
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IEEE 1076 Types VHDL is a strongly typed language (you cannot assign a signal of one type to the signal of another type) bit - a signal of type bit that can only take values of '0' or '1' bit_vector - a grouping of bits (each can be '0' or '1') SIGNAL a: BIT_VECTOR (0 TO 3); -- ascending range SIGNAL b: BIT_VECTOR (3 DOWNTO 0); -- descending range a <= "0111"; -- double quotes used for vectors b <= "0101"; This means that: a(0) = '0' b(0) = '1' a(1) = '1' b(1) = '0' a(2) = '1' b(2) = '1' a(3) = '1' b(3) = '0'
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INTEGER useful as index holders for loops, constants, generics, or high-level modeling BOOLEAN can take values ‘TRUE’ or ‘FALSE’ ENUMERATED has user defined set of possible values, e.g., TYPE traffic_light IS (green, yellow, red); IEEE 1076 TYPES (contd.)
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IEEE 1164 A package created to solve the limitations of the BIT type Nine values instead of just two ('0' and '1') Allows increased flexibility in VHDL coding, synthesis, and simulation STD_LOGIC and STD_LOGIC_VECTOR are used instead of BIT and BIT_VECTOR when a multi-valued logic system is required STD_LOGIC and STD_LOGIC _VECTOR must be used when tri-state logic (Z) is required To be able to use this new type, you need to add 2 lines to your code: LIBRARY ieee; USE ieee.std_logic_1164.ALL;
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1164 Types std_logic and std_logic_vector are the industry standard logic type for digital design Values for Simulation & Synthesis ‘0’ -- Forcing ‘0’ ‘1’ -- Forcing ‘1’ ‘Z’ -- High Impedance ‘L’ -- Weak ‘0’ ‘H’ -- Weak ‘1’ ‘-’ -- Don’t care Values for Simulation only (std_ulogic): ‘U’ -- Uninitialized ‘X’ -- Forcing Unknown ‘W’ -- Weak Unknown
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