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Unformatted text preview: (1 point) (1 point) (2 points) (2 points) (2 points) (2 points) (2 points) EE 20802 802 MIDTERM EXAM #1 Braun CLOSED BOOK + 1/2 Cheat Sheet
State any assumptions and show all work. Part 1 (10 Points) —
r . . Part 2 (16 Points) 
Print Your Name: dﬁﬂ M/i/ Part 3 (12 Points) —
Total (40 Points) — No unauthorized help given or received. Signature: For the purposes of today’s exam you may assume that the electron mobility in Silicon is 1000 cm“/Vs and
the hole mobility is 500 cm 2./Vs You may also assume for Silicon at room temperature that the intrinsic
carrier concentration, ni— — 1010 cm‘3 with B= 1.08 x 1031 cm 6K} 1. Semiconductor Fundamentals A region of Silicon has a donor concentration of 5x1017 crn'3 and an acceptor concentration of 2x1017 cm'3.
Please determine the following quantities at room temperature with VT: 0.025 V. A) Determine if the Silicon is N
lN—Type, MD _ M4 : 5xm’TM/S >> .2») 54?’ by M7 A/ ﬂ 2. Intrinsic,
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A) we? 4. None of the above B) The electron concentration. 7) : N2 /1/;? : 5x200”; ; dzxmiﬂ/W' ', C) The hole concentration. ,.2— /0 L
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JD ’ 0" ’ 495/03 2. PN Junction Diode A PN junction is formed between an ntype region of Silicon doped with a donor concentration of4x10I7 crn‘3
and a ptype region of Silicon doped with an acceptor concentration of 1016 cm'3. Please determine the
following quantities at room temperature with VT = 0.025 V. (2 points) A) The electrostatic potential in the ntype material, tbs“. . I7.~S
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(4)5” ; VT gm )7? : zsmi/Vn. iiﬁmﬂv"; , 0,114+ V (2 points) B) The electrostatic potential in the p—type material, tbsp. , ”r .£.~ _ "11f; »a 3¢§v
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(2 points) C) The built—in potential, (by
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r , 51/) J (2 points) D) Calculate the depletion laye_r width on the p—type side of the junction at zero bias.
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(2 points) E) Calculate the depletion layer width on tne n—type side of the junction at zero bias.
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r; 3,2 ZX/obi‘m ; 0, 5521/qu (2 points) (3) Calculate the total depletion layer width at a bias of +0.5 V applied to the pside with the n—side grounded. Leno"? : aiﬁtﬂm
(2 points) H) Calculate the total depletion layer width at a bias of 0.5 V applied to the pside with the nside grounded. (12 points) 3. Diode Logic Gate Please analyze the circuit shown to the left using the constant
voltage drop model with V0,, = 0.7 V. Determine the Qpoints for
each diode and the output voltage, VOW. }.iyﬂpvﬂff/gg ﬂ, )gg) 4,, WV Dﬁﬂw Ea C(T. bU/Th‘ (12/9 11/5/54 D2 +50V+—[:‘>‘—';:i «’2’!me :F
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 Spring '08
 BRAUN

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