# Midterm1S02 - (1 point(1 point(2 points(2 points(2 points(2...

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Unformatted text preview: (1 point) (1 point) (2 points) (2 points) (2 points) (2 points) (2 points) EE 208-02 802 MIDTERM EXAM #1 Braun CLOSED BOOK + 1/2 Cheat Sheet State any assumptions and show all work. Part 1 (10 Points) — r . . Part 2 (16 Points) - Print Your Name: dﬁﬂ M/i/ Part 3 (12 Points) — Total (40 Points) — No unauthorized help given or received. Signature: For the purposes of today’s exam you may assume that the electron mobility in Silicon is 1000 cm“/Vs and the hole mobility is 500 cm 2./Vs You may also assume for Silicon at room temperature that the intrinsic carrier concentration, ni— — 1010 cm‘3 with B= 1.08 x 1031 cm 6K} 1. Semiconductor Fundamentals A region of Silicon has a donor concentration of 5x1017 crn'3 and an acceptor concentration of 2x1017 cm'3. Please determine the following quantities at room temperature with VT: 0.025 V. A) Determine if the Silicon is N l-N—Type, MD _ M4 : 5xm’TM/S >> .2»)- 54?’ by M7 A/ ﬂ 2. Intrinsic, (Wear/4 7v 5 E AMI/\$77 5w 3. P-Type, or A) we? 4. None of the above B) The electron concentration. 7) : N2 -/1/;? : 5x200”; ; dzxmiﬂ/W' ', C) The hole concentration. ,.2— /0 L ”I [D 7(2’I4ys) V B 70 :1 H’ L ..__.-; : \$5 5 6 ”’4 g X [(7 612;; D) The conductivity. (W7 §i W; /’{,, 1,4 3/1/74 n) 3/61/17) .- (Lac/o" ()Z/[Wf‘ , 3pm” a»? / Lfg ‘%M7 E) The resistivity. “j/ v 5.1” : (720"? MJQ'C‘y JD ’ 0" ’ 495/03 2. PN Junction Diode A PN junction is formed between an n-type region of Silicon doped with a donor concentration of4x10I7 crn‘3 and a p-type region of Silicon doped with an acceptor concentration of 1016 cm'3. Please determine the following quantities at room temperature with VT = 0.025 V. (2 points) A) The electrostatic potential in the n-type material, tbs“. . I7.~S Wm _ ,. 4w W _/ " ' (4)5” ; VT gm )7? : zsmi/Vn. iiﬁmﬂv"; , 0,114+ V (2 points) B) The electrostatic potential in the p—type material, tbsp. , ”r-- .£.~ _ "11f; »a 3¢§v 41% I V7144 Z: , Vr/M p “ “25"42/ﬂ4 [/52an ’ 6’, (2 points) C) The built—in potential, (by . , _ , / 4; -4 ~43/” : £2455V+a3asw - QWQV r , 51/) J (2 points) D) Calculate the depletion laye_r width on the p—type side of the junction at zero bias. D0 P/‘M7 [3 HA5 1/ ‘A/ 0 a 5 22/147 ’ :: “fr- ': L . , ‘ ' - 290 i 1’ NA , lﬂ/ﬁzm'; 0' 314741;“ v‘“. ) r -—*-——-,7‘ -3 [W N» 4 x )0 (2 points) E) Calculate the depletion layer width on tne n—type side of the junction at zero bias. aka/£7 v0 5 22/11»; _ v —-———-':‘ — 7 " v KM ’ W " I (‘I-‘lelycilﬂrg _. f 8514/” + —’ J” ' ./ ”it? _ «a i Mr M ‘W’ .. 'r’. ﬂ X/O ﬂm (2 points) F) Calculate the total depletion layer width at zero bias. cmr“—*——’ EEEEEEEW%TT7TTTTTTTT—T we! 5 live/W » , Me a: 2.3V W":/ 3” (A27 4/5“) ¢J 1/ hex/V’QL tat/0'73”"; MW ‘5 319 r; 3,2 ZX/obi‘m -; 0, 5521/qu (2 points) (3) Calculate the total depletion layer width at a bias of +0.5 V applied to the p-side with the n—side grounded. Leno"? : aiﬁtﬂm (2 points) H) Calculate the total depletion layer width at a bias of -0.5 V applied to the p-side with the n-side grounded. (12 points) 3. Diode Logic Gate Please analyze the circuit shown to the left using the constant voltage drop model with V0,, = 0.7 V. Determine the Q-points for each diode and the output voltage, VOW. }.iyﬂpvﬂff/gg ﬂ, )gg) 4,, WV Dﬁﬂw Ea C(T. bU/Th‘ (12/9 11/5/54 D2 +50V+—[:‘>‘—';:i «’2’!me :F 131/4 I} le «.‘l [W IL’KJZ v 4 5) l/ _ _ _ 4 (VI-i7: All—4% “#:IIZT Vavr 51/2/51; tag/E , isz I?) 13W \/ C\'/ 1/, l-TL ~ a>v ~ {LS} V”, _. / wu ' / if )2 '7" : IQL’~%§L : (27’7/M/y '3’ 8‘ )M’IL __ V6; - um ~ tau; , Zia/Z3515“ , [4)»47/7 I; : J; : W ' 2,207, ~ _ , a [2572 ﬂ ; [7, 599M747 , - ) * A 45“?” I ’ I l ~ I2 (7" . .« V‘ ‘ ‘11 : 9171/ \V/ " Val/4,1; + 1; ‘iA/J‘Z ‘: Q?I//>P //‘%§IV/7y///i > 92 M7 , , t , / ALL H‘//7(/7#£§ES 7'59 7' v &, / S”L/ ...
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