Chapter08

Microelectronic Circuit Design

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CHAPTER 8 8.1 ( a ) 256Mb = 2 8 2 10 () 2 10 = 268,435,456 bits (b) 1Gb = 2 10 ( ) 3 = 1,073,741,824 bits c 256Mb = 2 8 2 10 2 10 =2 28 | 128kb = 2 7 2 10 = 2 17 | 2 28 2 17 = 2 11 = 2048 blocks 8.2 I 1 mA 2 28 bits = 3.73 pA bit 8.3 a P = CV DD 2 f = 64 10pF ( ) 3.3 ( ) 2 1 GHz ( ) = 6.97 W b P = CV DD 2 f =6410 pF 2.5 2 3 GHz = 12 W 8.4 P = CV DD 2 f = 2 30 2 100fF 2.5 V 2 1 0.012 s = 28.0 m W 8.5 "1" = V DD = 3 V "0": 3 V O 10 10 = 2 1 100 x 10 6 3 0.75 V O 2 V O V O = 0.667 µ V "0"= 0.667 V 8-1
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8.6 *PROBLEM 8.6 - 6-T Cell VDD 1 0 DC 3 MN1 3 2 0 0 MOSN W=4U L=2U AS=16P AD=16P MP1 3 2 1 1 MOSP W=10U L=2U AS=40P AD=40P MN2 2 3 0 0 MOSN W=4U L=2U AS=16P AD=16P MP2 2 3 1 1 MOSP W=10U L=2U AS=40P AD=40P MN3 3 0 0 0 MOSN W=4U L=2U AS=16P AD=16P MN4 2 0 0 0 MOSN W=4U L=2U AS=16P AD=16P .IC V(3)=1.55V V(2)=1.45V V(1)=3 .OP .TRAN 0.025N 10N UIC .MODEL MOSN NMOS KP=5E-5 VTO=0.91 GAMMA=0.99 +LAMBDA=.02 TOX=41.5N +CGSO=330P CGDO=330P CJ=3.9E-4 CJSW=510P .MODEL MOSP PMOS KP=2E-5 VTO=-0.77 GAMMA=0.5 +LAMBDA=.05 TOX=41.5N +CGSO=315P CGDO=315P CJ=2.0E-4 CJSW=180P .PRINT TRAN V(2) V(3) .PROBE V(2) V(3) .END 0s 2ns 4ns 6ns 8ns 10ns Time 4.0V 3.0V 2.0V 1.0V 0V -1.0V Result: t = 1.5 ns 8-2
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8.7 3 V 1.5 V 0.7 V 2.3 V (a) 3 V 0.7 V 2.3 V 1.5 V +3 V (b) First Case : Both transistors are in the linear region I DS = 25 x 10 6 1 1 2.3 0.7 0.7 2 0.7 = 21.88 µ A 21.88 A = 25 x 10 6 W L 3 0.7 0.7 0.8 2 0.8 W L 0.911 = 1 1.10 Second Case : Both transistors are in the linear region 10 x 10 6 1 1 0.7 3 −− 0.7 () 0.7 2 0.7 = 25 x 10 6 W L 3 1.5 0.7 0.8 2 0.8 W L 1.09 1 So W L 1 1.10 8-3
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8.8 *Problem 8.8 - WRITING THE CMOS SRAM VWL 6 0 DC 0 PULSE(0 3 1NS 1NS 1NS 100NS) VDD 3 0 DC 3 VBL1 4 0 DC 0 VBL2 5 0 DC 3 CBL1 4 0 500FF CBL2 5 0 500FF *Storage Cell MCN1 2 1 0 0 MOSN W=1U L=1U AS=4P AD=4P MCP1 2 1 3 3 MOSP W=1U L=1U AS=4P AD=4P MCN2 1 2 0 0 MOSN W=1U L=1U AS=4P AD=4P MCP2 1 2 3 3 MOSP W=1U L=1U AS=4P AD=4P MA1 4 6 2 0 MOSN W=1U L=1U AS=4P AD=4P MA2 5 6 1 0 MOSN W=1U L=1U AS=4P AD=4P * .OP .TRAN 0.01NS 20NS .NODESET V(1)=3 V(2)=0 .MODEL MOSN NMOS KP=2.5E-5 VTO=.70 GAMMA=0.5 +LAMBDA=.05 TOX=20N +CGSO=4E-9 CGDO=4E-9 CJ=2.0E-4 CJSW=5.0E-10 .MODEL MOSP PMOS KP=1.0E-5 VTO=-.70 GAMMA=0.75 +LAMBDA=.05 TOX=20N +CGSO=4E-9 CGDO=4E-9 CJ=2.0E-4 CJSW=5.0E-10 .PROBE V(1) V(2) V(3) V(4) V(5) V(6) .END 0s 2ns 4ns 6ns 8ns 10ns Time 4.0V 3.0V 2.0V 1.0V 0V -1.0V Small voltage transients occur on both cell storage nodes which die out in 5 - 7 ns. 8-4
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8.9 a () The transistor will fully discharge C C : V C 0 = 0 V V C 1 = 2.5 V TN = 2.5 0.6 0.5 V C 1 + 0.6 0.6 V C 1 = 1.55 V | "1"= 1.55 V For V C1 = 2.5 V , V TN = 0.6 + 0.5 2.5 + 0.6 0.6 = 1.09 V | V W/L 2.5 + 1.09 = 3.59 V 8.10 For "0" = 0V, the bias across the source-substrate junction is 0 V, so the leakage current would be 0 and the "0" state is undisturbed. For a "1" corresponding to a positive voltage, a reverse bias across the source-substrate junction, and the diode leakage current will tend to destroy the "1" state.
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Chapter08 - CHAPTER 8 8.1 (a) 256Mb = 28 210 210 =...

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