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**Unformatted text preview: **Exam 1 CPE 229/269 j gh 2/2/07
Name §ol EH 0V\S (50 min.) open text CPE 229/269 Reader (lOOpts) I have neither been given nor have received during this exam unauthorized assistance per
the university policy on cheating. Signature l.(10) State the ﬁve axioms and their duals that deﬁne the Boolean algebra (21). 10“ X:O "5‘x*¢ ’6‘ wet éxwo
20‘ \Sr XTOJ’Hov‘izl 2(1‘ we x:|)mg;o
3Q. 0‘70 =0 31:“ cL+L=1
4a 1-4:=’l. 45, O+O=o 5a. 0431030 31,. 1+0 = o+1=1 2.(lO) Given the following truth table for the Boolean function f and its variables a, b,
and c, showing all steps in your solution, implement the logic function f as a function of
the variables a, b, and c with a logic diagram using NOT, AND, and OR gates. 4 Ma
\oyc +4 ‘ 3. Given the template VHDL code, complete the code for the architecture declaration
using the dataﬂow style indicated for the logic equation f = (lx - y - z) + (x - y - lz)
where lb => not b. Don't forget to relate the function variables to the VHDL variables.
: ' Mich "l‘lxe/e we 0% Sow-1mg "Wm Qer bell ow),
\a’l‘ m2); : y 0‘0) 2 3 a to) = 3 library IEEE;
use IEEE.STD_LOGIC_1 164.2111; entity prob3 is port ( W
a: in std_logic_vector (2 downto O); f: out std_logic );
end prob3; {Xi‘an}: 71%va : 5(a) «(ma—('01.
awed}: 'xl‘tfr am» “03410) a.(10) simple signal assignment (Boolean equations) architecture dataﬂow of prob3 is
begin Q— < =<Lwo+ on») w an) M 6(0)) W (“23W ‘3“) “’9 (Ml mo“); end dataﬂow;
b.(10) conditional signal assignment (when-else statement) architecture dataﬂow of prob3 is
begin
H M \\ \\
$y<—,\i‘ wW<(Q:\\O\\)o\/~ (Ck— \\O )dez end dataﬂow; c.(10) selected signal assignment (with—select-When statement) architecture dataﬂow of prob3 is
begin @\ MM —s
an {12mm ,5
aka) ~3‘ end dataﬂow; 1 4. (25) Given the template VHDL code, implement the synchronous ﬁnite state machine
deﬁned by the state diagram given below using the two process PS/N S method. Deﬁne
any signals that are needed to complete your implementation. library IEEE;
use IEEE.STD_LOGIC_1 164.all; entity prob4 is port (
x, clk: in std_logic;
f: out std_logic
); end prob4; -' - Simdci \oe logl/axltowagslmporbo’vci‘ “gar ATooiS architecture behavior‘of prob4 is
‘irql’e siméq‘ix‘ee is (32m) 0M2) 41.13 ) alt/or);
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W toe/Md VS7-BYM 1) 'éké‘ Case; g emu (Drones: cowlo - pvuc‘J end behavior;~ 5. The VHDL code for a clocked synchronous ﬁnite state machine is given below.
Showing all steps and all deﬁnitions required in your solution, determine the:
a.(15) draw a logic diagram which implements the state machine with D ﬂip-ﬂops. library IEEE;
use IEEE.STD_LOGIC_1 164.2111; entity probS is port (
X, clk: in std__logic;
z: out std_logic
); end probS; architecture dataﬂow of prob5 is signal d: std_logic; signal q: std_logic; begin d <= not (q and x); 2 <= (not q) or x; q <= (1 when rising_edge(clk) else
q; end dataﬂow; b.(10) state diagram indicating whether it is a Mealy or Moore architecture a t c): '1 (Q
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- Spring '08
- HARRIS
- Boolean Algebra, Boolean function, architecture dataflow, template VHDL code, synchronous ﬁnite state