Exam2_solutions - CPE 229 Your name(please print I have not...

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1 CPE 229 Exam 2 Your name _________________________________________ (please print) I have not received or given unauthorized assistance for this exam._________________________________ (your signature) 1. a (16) Use good programming practice and fill in the architecture declaration in the following VHDL code for the circuit in Figure 1 using the Two Process PS/NS method: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Prob1 is Port ( init, clk, x : in STD_LOGIC; z1, z2, z3 : out STD_LOGIC; y : out STD_LOGIC_VECTOR (1 downto 0) ); end Prob1; architecture Behavioral of Prob1 is type state_type is (s0, s1); signal ps, ns : state_type; begin syn_process: process (init, clk) begin if init = '1' then ps <= s0; elsif rising_edge (clk) then ps <= ns; end if; end process; comb_process: process (ps,x) begin z1 <= '0'; z2 <= '0'; z3 <= '1'; -- default Moore and Mealy outputs case ps is when s0 => y <= "01"; z1 <= '1'; ns <= s1; when s1 => y <= "10"; if x = '1' then ns <= s0; z3 <= '0'; else ns <= s1; z2 <= '1'; end if; end case; end process; end Behavioral; b (4) Name the type of encoding that is used for the FF outputs in Figure 1. One-hot encoding is used c (2) Name the signal convention that is used for listing Moore and Mealy outputs in Figure 1.
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