1CPE 229Exam 1Your name _________________________________________(please print)I have not received or given unauthorized assistance for this exam._________________________________(your signature)1.Write a dataflow architecture declaration for the counter circuit in Figure 1. Use one conditional signalassignment with an aggregate. PRE is a clock independent input.Figure 1Answer: Listing 1 shows the dataflow architecture declaration for the counter circuit using oneconditional signal assignment with an aggregate.architecturedataflowofcounterisbeginq <= "11"whenset = '1'else(q(1)xnorq(0),notq(0))whenrising_edge (clk);enddataflow;Listing 1Remember that the placement of the elements (or the order of the element) in the aggregate is veryimportant2.Name the three parts of a design entity in VHDL?Answer: Library part, entity declaration and architecture declaration3.Write anentity declarationfor MUX4_1 in Figure 3 with scalar input signals.DQCQ1Q0D0D1PREDQCCLKPRESET(asyn)SET(asyn)CLKQ0QQ10
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