Midterm_Exam_solutions - CPE 229 Your name(please print I...

Info icon This preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
1 CPE 229 Exam 1 Your name _________________________________________ (please print) I have not received or given unauthorized assistance for this exam._________________________________ (your signature) 1. Write a dataflow architecture declaration for the counter circuit in Figure 1. Use one conditional signal assignment with an aggregate. PRE is a clock independent input. Figure 1 Answer : Listing 1 shows the dataflow architecture declaration for the counter circuit using one conditional signal assignment with an aggregate. architecture dataflow of counter is begin q <= "11" when set = '1' else (q(1) xnor q(0), not q(0)) when rising_edge (clk); end dataflow; Listing 1 Remember that the placement of the elements (or the order of the element) in the aggregate is very important 2. Name the three parts of a design entity in VHDL? Answer : Library part, entity declaration and architecture declaration 3. Write an entity declaration for MUX4_1 in Figure 3 with scalar input signals. D Q C Q 1 Q 0 D 0 D 1 PRE D Q C CLK PRE SET (asyn) SET (asyn) CLK Q 0 Q Q 1 0
Image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon