Midterm_Exam_solutions

Midterm_Exam_solutions - CPE 229 Your name(please print I...

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1 CPE 229 Exam 1 Your name _________________________________________ (please print) I have not received or given unauthorized assistance for this exam._________________________________ (your signature) 1. Write a dataflow architecture declaration for the counter circuit in Figure 1. Use one conditional signal assignment with an aggregate. PRE is a clock independent input. Figure 1 Answer : Listing 1 shows the dataflow architecture declaration for the counter circuit using one conditional signal assignment with an aggregate. architecture dataflow of counter is begin q <= "11" when set = '1' else (q(1) xnor q(0), not q(0)) when rising_edge (clk); end dataflow; Listing 1 Remember that the placement of the elements (or the order of the element) in the aggregate is very important 2. Name the three parts of a design entity in VHDL? Answer : Library part, entity declaration and architecture declaration 3. Write an entity declaration for MUX4_1 in Figure 3 with scalar input signals. D Q C Q 1 Q 0 D 0 D 1 PRE D Q C CLK PRE SET (asyn) SET (asyn) CLK Q 0 Q Q 1 0
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2 F 00 01 10 11 D 0 D 1 D 2 D 3 S 1 S 0 Figure 3 Answer : Listing 3 shows the entity declaration for MUX4_1 with scalar input signals. entity MUX4_1 is port ( S1, S0, D0, D1, D2, D3: in std_logic; F: out std_logic ); end MUX4_1; Listing 3 4. Write complete VHDL code using a when-else statement for the 2-bit comparator circuit in Figure 4 which compares D 1 D 0 with B 1 B 0 to see if they have the same values, if so F = 1, else F = 0. D0 D1 F B1 B0 D_B0 D_B1 Figure 4 Answer : Listing 4 shows the dataflow architecture declaration for the 2-bit comparator using a when-else statement . library IEEE; use IEEE.STD_LOGIC_1164. all ; Entity comparator is port ( D0,B0,D1,B1: in std_logic; F: out std_logic ); End comparator;
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3 architecture dataflow of comparator is begin F <= '1' when (D0 xnor B0) = '1' and (D1 xnor B1) = '1 else '0'; end dataflow; Listing 4 5. Use the PS/NS Tabular Method to write a behavioral architecture declaration for the counter shown in Table 5 using DFFs. Signal SET is a clock dependent signal. 1 0 Q Q 1 1 1 0 0 1 0 0 SET (syn) Table 5 Answer : Listing 5 shows the behavioral architecture declaration for the counter represented with a clock dependent input named SET architecture behavioral of counter is begin process (clk) begin if rising_edge (clk) then if set = '1' then q <= "11"; else case q is when "11" => q <= "10"; when "10" => q <= "01"; when "01" => q <= "00"; when "00" => q <= "11"; when others => null ; end case ; end if ; end if ; end process ; end behavioral; Listing 5 Since the signal SET is dependent on the clock, the signal SET must occur in the VHDL code after rising_edge (clk). 6. Use the Algorithmic Equation Method to obtain the schematic for the counter shown in Table 6 using DFFs. What would be an appropriate name for this counter?
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4 1 0 Q Q 1 1 1 0 0 1 0 0 RST (asyn) Table 6 Answer : Using the Set OR Hold 1 Equation we can write the following D excitation equations: 0 1 0 + 1 0 = 0 1 1
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Midterm_Exam_solutions - CPE 229 Your name(please print I...

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