68000 Instr Set

68000 Instr Set - The 68000's Instruction Set We have...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
W e have included this appendix to save you the task of having to turn to secondary material when writing 68000 assembly language programs. Since most programmers are not interested in the encoding of instructions, details of instruction encoding have been omitted (i.e., the actual op-code bit patterns). Applications of some of the instructions have been provided to demonstrate how they can be used in practice. Instructions are listed by mnemonic in alphabetical order. The information provided about each instruction is: its assembler syntax, its attributes (i.e., whether it takes a byte, word, or longword operand), its description in words, the effect its execution has on the condition codes, and the addressing modes it may take. The effect of an instruction on the CCR is specified by the following codes: U The state of the bit is undefined (i.e., its value cannot be predicted) - The bit remains unchanged by the execution of the instruction * The bit is set or cleared according to the outcome of the instruction. Unless an addressing mode is implicit (e.g., NOP , RESET , RTS , etc.), the legal source and destination addressing modes are specified by their assembly language syntax. The following notation is used to describe the 68000’s instruction set. Dn, An Data and address register direct. (An) Address register indirect. (An)+, -(An) Address register indirect with post-incrementing or pre- decrementing. (d,An), (d,An,Xi) Address register indirect with displacement, and address register indirect with indexing and a displacement. ABS.W, ABS.L Absolute addressing with a 16-bit or a 32-bit address. (d,PC), (d,PC,Xi) Program counter relative addressing with a 16-bit offset, or with an 8-bit offset plus the contents of an index register. imm An immediate value (i.e., literal) which may be 16 or 32 bits, depending on the instruction. 1 The 68000’s Instruction Set
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
2 The 68000’s Instruction Set Two notations are employed for address register indirect addressing. The notation originally used to indicate address register indirect addressing has been superseded. However, the Teesside 68000 simulator supports only the older form. Old notation Current notation d(An), d(An,Xi) (d,An), (d,An,Xi) d(PC), d(PC,Xi) (d,PC), (d,PC,Xi) ABCD Add decimal with extend Operation: [destination] 10 [source] 10 + [destination] 10 + [X] Syntax: ABCD Dy,Dx ABCD -(Ay),-(Ax) Attributes: Size = byte Description: Add the source operand to the destination operand along with the extend bit, and store the result in the destination location. The addition is performed using BCD arithmetic. The only legal addressing modes are data register direct and memory to memory with address register indirect using pre-decrementing. Application:
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

Page1 / 58

68000 Instr Set - The 68000's Instruction Set We have...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online