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Unformatted text preview: word and the remainder is the upper-order word. DIVU performs division on unsigned values, and DIVS performs division on two±s complement values. An attempt to divide by zero causes an exception. For DIVS , the sign of the remainder is always the same as the sign of the dividend (unless the remainder is zero). Attempting to divide a number by zero results in a divide-by-zero exception. If overflow is detected during division, the operands are unaffected. Overflow is checked for at the start of the opera-tion and occurs if the quotient is larger than a 16-bit signed inte-ger. If the upper word of the dividend is greater than or equal to the divisor, the V-bit is set and the instruction terminated. Application: Consider the division of D0 by D1, DIVU D1,D0 , which results in: [D0(0:15)] ← [D0(0:31)]/[D1(0:15)] [D0(16:31)] ← remainder...
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This note was uploaded on 03/05/2008 for the course EE 357 taught by Professor Mayeda during the Spring '08 term at USC.
- Spring '08