3504notes_p3 - (excitation equation of d-flipflop Universal...

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ROMs 2^n addresses n address lines up to 2^n addresses 8 addresses is controlled by 3 address lines k bits per address we need k data lines Any memory module that has 2^k addresses X m bits/address k addresses line and m data lines /* Logic: examples of simple gates expressed in CUPL */ inva = !a; /* inverters */ invb = !b; and = a & b; /* and gate */ nand = !(a & b); /* nand gate */ or = a # b; /* or gate */ xor = a $ b; /* xor gate */ nor = !(a # b); /* nor gate */ xnor = 1(a $ b); /* exclusive nor gate */ PIN 22 = output1 PIN 23 = output2 output1 = (in1&!in2)#(in3&in4); output2.D = (in3 & in2) $ (in5 # in6);
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Unformatted text preview: /* (excitation equation of d-flipflop) */ Universal Shift Register depends on S1 S0 AA BB CC DD QA QB QC QD RIN LIN QA+ QB+ QC+ QD+ Iterative Design (Qi+=) A4 A3 A2 A1 Rin Lin Q4 Q3 Q2 Q1 S1 S0 I Є{1,2,3,4} Qi+ = S1’ SO’ ( Qi ) + S1’ SO ( Qi+1 ) + S1 SO’ ( Qi-1 ) + S1 SO ( Ai ) when i=4 make Qi+4 Rin depending on the type of shift (arithmetic, logic, circular, etc) Headers: Name UnivShft; PartNo 01; Date 8/20/02; Revision 01; Designer Will Johnson; Company Virginia Tech; Assembly None; Location ; Device P22v10; /* This line is required */...
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This note was uploaded on 05/23/2008 for the course ECE 3504 taught by Professor Jsthweatt during the Summer '06 term at Virginia Tech.

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