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n_23462 - Chapter 3: Pipelining Review instruction format...

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ECE-C-621 Chapter 3 Class notes 1/44 Chapter 3: Pipelining Review instruction format ECE-C-621 Chapter 3 Class notes 2/44 Look at simple non-pipelined implementation first Multiple-Cycle DLX: DLX instructions can be implemented in 5 clock cycles The first two clock cycles are the same for all instructions 1. Instruction fetch cycle (IF) IR ± Mem[PC] (load instruction) NPC ± PC+4 (update program counter) 2. Instruction decode / register fetch cycle (ID) A ± Regs[IR 6...10 ] (fetch source reg1) B ± Regs[IR 11. ..15 ] (fetch source reg2) Imm ± (IR 16 ) 16 ## IR 16. ..31 (fetch and sign-ext imm) Cycle 3: Execution/ effective address cycle (EX) The actions performed in this cycle depend on the type of operations. Memory reference (e.g., LW R1, 30 (R2)) ALUOutput ± A + Imm (Calculate effective address) Register-Register ALU op. (e.g., ADD R1, R2, R3) ALUOutput ± A op B (Perform ALU operation) Register-Immed. ALU op. (e.g., ADD R1, R2, #3) ALUOutput ± A op Imm (Perform ALU operation) Branch (e.g., BEQZ R4, next) ALUOutput ± NPC + Imm (Compute branch target) Cond ± (A == 0) (Compare A to 0) ECE-C-621 Chapter 3 Class notes 3/44 Cycle 4: Memory access / branch completion cycle (MEM) The only DLX instructions active in this cycle are loads, stores, and branches Loads (e.g., LW R1, 30 (R2)) LMD ± Mem[ALUOutput] (load memory onto processor) Stores (e.g., 500(R4), R3) Mem[ALUOutput] ± B (store data into memory) Branch (e.g., BEQZ R4, next) if (cond) PC ± ALUoutput (Set PC based on cond) else PC ± NPC Cycle 5: Write-back cycle (WB) During this cycles, results are written to the register file Register-Register ALU op. (e.g., ADD R1, R2, R3) Regs[IR 16. ..20 ] ± ALUOutput Register-Immed. ALU op(e.g., ADD R1, R2, #3) Regs[IR 11. ..15 ] ± ALUOutput Load Instruction (e.g., LW R1, 30 (R2)) Regs[IR 11. ..15 ] ± LMD ECE-C-621 Chapter 3 Class notes 4/44
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ECE-C-621 Chapter 3 Class notes 5/44 ECE-C-621 Chapter 3 Class notes 6/44 CPI for the Multiple-Cycle DLX The multiple-cycle DLX requires 4 cycles for branches and stores and 5 cycles for the other operations. Assuming 17% of the instructions are branches or loads, this gives a CPI of 4.83. We could improve the CPI by allowing ALU operations to complete in 4 cycles. Assuming 47% of the instructions are ALU operations, this would reduce the CPI to 4.36. ECE-C-621 Chapter 3 Class notes 7/44 Pipelining DLX To reduce the CPI, DLX can be implemented using a five stage pipeline. Figure 3.2 Here, it takes 10 cycles to execute 5 instructions for a CPI of 2. ECE-C-621 Chapter 3 Class notes 8/44 Visualizing Pipelining Figure 3.3 Why does it work? Use separate I and D caches Register file can be read/written in 0-5 cycles PC: incremented in IF if branch taken, in MEM, add PC+Imm Cannot keep any state in IR ± need to move it to another register every cycle (see Figure 3.4) Registers IF/ID, ID/EX, EX/MEM, MEM/WB replace the temporary registers
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ECE-C-621 Chapter 3 Class notes 9/44 Pipelined DLX Datapath
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This note was uploaded on 05/10/2008 for the course EE 465 taught by Professor Chow during the Winter '04 term at USC.

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n_23462 - Chapter 3: Pipelining Review instruction format...

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