ch8 - SEQUENTIAL NETWORKS CANONICAL FORM OF SEQUENTIAL...

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1 SEQUENTIAL NETWORKS CANONICAL FORM OF SEQUENTIAL NETWORKS LATCHES AND EDGE-TRIGGERED CELLS. D FLIP-FLOP TIMING CHARACTERISTICS ANALYSIS AND DESIGN OF CANONICAL NETWORKS SR, JK and T FLIP-FLOP ANALYSIS OF FLIP-FLOP NETWORKS DESIGN OF FLIP-FLOP NETWORKS. EXCITATION FUNCTIONS SPECIAL STATE ASSIGNMENTS: ONE-FLIP-FLOP-PER-STATE AND SHIFT- ING REGISTER Introduction to Digital Systems 8 – Sequential Networks
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2 CANONICAL FORM OF SEQUENTIAL NETWORKS (Huffman-Moore) State-transition function s ( t + 1) = G ( s ( t ) , x ( t )) Output function z ( t ) = H ( s ( t ) , x ( t )) (a) CLK z(t) State Register s(t) s(t+1) x(t) initialize Combinational Network present input present state next state present output (b) t Ideal clock 0 1 2 3 4 5 6 7 t PRESENT STATE s(t) NEXT STATE s(t+1) Ideal clock pulse Figure 8.1: a) CANONICAL IMPLEMENTATION OF SEQUENTIAL NETWORK. b) IDEAL CLOCK SIGNAL AND ITS INTERPRE- TATION. Introduction to Digital Systems 8 – Sequential Networks
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3 MEALY AND MOORE MACHINES (a) (b) CLK x(t) CLK C1 C2 State Register s(t+1) s(t) s(t+1) s(t) C1 State Register z(t) C2 z(t) x(t) Figure 8.2: CANONICAL IMPLEMENTATIONS: a) MEALY MACHINE. b) MOORE MACHINE. Introduction to Digital Systems 8 – Sequential Networks
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4 HIGH-LEVEL AND BINARY IMPLEMENTATIONS CLK State Register (binary cells) Y 0 Y 1 Y k-1 y 0 y 1 y k-1 z 0 z n-1 x m-1 x 0 Combinational Network Initialize Inputs Outputs Next state Present state Figure 8.3: CANONICAL IMPLEMENTATION WITH BINARY VARIABLES. Introduction to Digital Systems 8 – Sequential Networks
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5 EXAMPLE 8.1 Input: x ( t ) = ( x 1 , x 0 ) , x i ∈ { 0 , 1 } Output: z ( t ) ∈ { 0 , 1 } State: y ( t ) = ( y 3 , y 2 , y 1 , y 0 ) , y i ( t ) ∈ { 0 , 1 } Initial state: y (0) = (0 , 0 , 0 , 0) Function: The transition and output functions Y 3 = y 2 x 0 1 x 0 Y 2 = ( y 1 y 2 ) x 0 0 y 3 x 1 Y 1 = ( y 0 y 3 ) x 0 1 x 0 ( y 0 y 1 ) x 1 Y 0 = ( y 0 y 3 ) x 0 0 y 1 x 0 1 x 0 y 2 x 1 z = y 3 y 2 y 1 y 0 Introduction to Digital Systems 8 – Sequential Networks
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6 EXAMPLE 8.1 (cont.) CLK Y 0 Y 1 y 0 y 1 z x 0 Combinational Network Initialize Y 2 Y 3 y 2 y 3 x 1 Figure 8.4: CANONICAL NETWORK FOR EXAMPLE 8.1. Introduction to Digital Systems 8 – Sequential Networks
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7 CLOCK clock period T clock frequency f = 1 /T (clock) pulse width t w CLK t w Clock pulse width Clock period T time Figure 8.5: PULSE WIDTH AND CLOCK PERIOD. Introduction to Digital Systems 8 – Sequential Networks
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8 GATED LATCH - FIRST TRY (a) Q D E (b) D t p E Q t p Figure 8.6: a) GATED-LATCH. b) TIMING BEHAVIOR. Q ( t + t p ) = D ( t ) · E ( t ) Q ( t ) · E 0 ( t ) LEVEL-SENSITIVE: when E = 1 then Q = D Introduction to Digital Systems 8 – Sequential Networks
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9 nor - nor LATCH Q E D a b c d (b) + * c kept in 0 even when b=0 + Q kept in 0 even when d=0 D E Q a b c d (Input) (Enable) (Output) (a) loop * loop Figure 8.7: a) IMPLEMENTATION OF GATED-LATCH WITH nor GATES. b) TIMING DIAGRAM. Introduction to Digital Systems 8 – Sequential Networks
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10 LATCH WITH TRANSMISSION GATES Q E D a b c d (b) Q D E (Output) (Enable) (Input) a b c d e f TG1 TG2 on off on off TG1 TG2 f (a) loop loop Figure 8.8: a) IMPLEMENTATION OF GATED-LATCH WITH TRANSMISSION GATES. b) TIMING DIAGRAM.
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