{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

ch12 - PROGRAMMABLE MODULES SPECIFICATION OF PROGRAMMABLE...

Info iconThis preview shows pages 1–10. Sign up to view the full content.

View Full Document Right Arrow Icon
1 PROGRAMMABLE MODULES SPECIFICATION OF PROGRAMMABLE COMBINATIONAL AND SEQUENTIAL MODULES 1. psa 2. rom 3. fpga THE WAY THE MODULES ARE PROGRAMMED NETWORKS OF PROGRAMMABLE MODULES EXAMPLES OF USES Introduction to Digital Systems 12 – Programmable Modules
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
2 PROGRAMMABLE SEQUENTIAL ARRAYS ( psa ) PLA State register clk z x Y y k p n p next state present state inputs outputs PSA Figure 12.1: PROGRAMMABLE SEQUENTIAL ARRAY ( psa ). Introduction to Digital Systems 12 – Programmable Modules
Background image of page 2
3 Example 12.1: IMPLEMENTATION OF SEQUENTIAL SYSTEMS USING psa s SEQUENCE GENERATOR INPUTS: x ∈ { 0 , 1 } OUTPUTS: z ∈ { 0 , 1 , 3 , 6 , 7 , 10 , 14 } FUNCTION: The transition and output functions x = 0 : z = 0 10 14 7 0 · · · x = 1 : z = 1 10 3 6 1 · · · x = 0 : z = 0000 1010 1110 0111 0000 · · · x = 1 : z = 0001 1010 0011 0110 0001 · · · Introduction to Digital Systems 12 – Programmable Modules
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
4 CLK z 3 z 2 z 1 z 0 0 0 0 0 1 0 1 0 1 1 1 0 0 1 1 1 State CLK z 3 z 2 z 1 z 0 State 0 0 0 1 1 0 1 0 0 0 1 1 0 1 1 0 (a) Case x = 0 (b) Case x = 1 0 10 14 7 0 10 14 7 1 10 3 6 1 10 3 6 Figure 12.2: TIMING SEQUENCES IN Example 12.1. Introduction to Digital Systems 12 – Programmable Modules
Background image of page 4
5 Example 12.1 (cont.) y k = 0 k = 1 0 10 - k 1 - 10 k 3 - 6 x 6 0 1 k 7 0 1 k 10 14 3 k 14 7 - x Y K y ∈ { 2 , 4 , 5 , 8 , 9 , 11 , 12 , 13 , 15 } – don’t care states K = xy 3 y 2 xy 0 3 y 0 2 y 1 ky 0 1 ky 0 3 y 2 ky 3 y 0 2 Y 3 = y 0 1 y 0 2 k 0 Y 2 = y 0 3 y 0 2 y 1 y 3 k 0 Y 1 = y 0 2 y 3 Y 0 = y 3 k y 2 k y 3 y 2 Introduction to Digital Systems 12 – Programmable Modules
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
6 11 12 13 y 3 k y 3 k’ y’ 2 k’ output K STATE REGISTER next state present state CLK 9 14 x 15 16 17 18 y 3 y 2 x y’ 3 y’ 2 y 1 k y’ 1 k y’ 3 y 2 k -- programmable connection y 3 -- connection made y 2 y 1 y 0 (from state register) x k 9 10 y’ y 3 y 2 y’ 2 y 1 y 0 5 6 7 8 y 2 k 1 y’ 2 y 3 1 2 3 4 5 6 8 7 Y 1 Y 0 Y 2 Y 3 1 2 4 3 z 0 z 1 z 2 z 3 y 1 y 0 y 2 y 3 y 3 y’ 2 k Figure 12.3: psa IMPLEMENTATION IN Example 12.1. Introduction to Digital Systems 12 – Programmable Modules
Background image of page 6
7 READ-ONLY MEMORIES ( rom ) Address Inputs Outputs x n-1 z k-1 x 1 x 0 z 0 ROM k X 2 n En E Figure 12.4: READ-ONLY MEMORY ( rom ) Introduction to Digital Systems 12 – Programmable Modules
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
8 EXAMPLE 12.2 Address Contents x z 000 1011 001 1101 010 0111 011 1000 100 0000 101 1111 110 1111 111 1011 Introduction to Digital Systems 12 – Programmable Modules
Background image of page 8
9 x 1 x 0 E z 1 z 0 z 2 z 3 0 1 0 1 1 1 0 0 1 0 1 1 0 0 1 0 0 0 0 1 1 0 1 1 1 1 1 1 0 - - Z Z Z Z Gnd NOR Array Gnd Gnd 0 1 0 1 1 1 0 1 1 0 1 0 0 0 1 0 0 1 2 3 1 0 word 0 word 1 word 2 word 3 pull-up devices Vdd x 1 x 0 enable Binary decoder three-state buffers E z
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Image of page 10
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}