EE 201L - Lab Plan for Spring 2008 -- under revision Date: 1/18/2008Note: The following three labs from Fall 2007 are removed to make space for the new labs.Lab #2 Characteristics of TTL Gates, Lab #8 Debugging via prototyping using Logic Analyzer, Lab 9: Static and Dynamic Hazards (take home lab)Week #DateLab NumberLab sessionHome assignmentsWeek 1Jan. 15-18Lab # 0Introduction to lab equipmentPrelab for Lab # 1 Week 2Jan. 22-25Lab # 1Voting machineWatch lecture on ePD (video) + ePD_Demo + Prelab for Lab # 3Week 3Jan. 29-Feb 1Lab # 3Intro. to Electronic Product Designer (ePD) Lab4a: Multiplexers & Prelab for Lab # 5Week 4 Feb. 5-8Lab # 5Debugging via simulation using ePDIntroduction to FPGAsPrelab for Lab # 6, also perform steps 6.1 and 6.2 of the procedure and complete the “core” of the DETOUR design and simulate. Install Xilinx and ModelSim on your Home PCWeek 5Feb. 12-15Lab # 6, Lab #7Implementation of Detour signal lab on the FPGA boardLab 7: Number lock (Try to finish Number Lock in lab)Complete the Number lock at home.
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