EE201_Plan_Spring2008_draft

EE201_Plan_Spring2008_draft - EE 201L - Lab Plan for Spring...

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EE 201L - Lab Plan for Spring 2008 -- under revision Date: 1/18/2008 Note: The following three labs from Fall 2007 are removed to make space for the new labs. Lab #2 Characteristics of TTL Gates, Lab #8 Debugging via prototyping using Logic Analyzer, Lab 9: Static and Dynamic Hazards (take home lab) Week # Date Lab Number Lab session Home assignments Week 1 Jan. 15-18 Lab # 0 Introduction to lab equipment Prelab for Lab # 1 Week 2 Jan. 22-25 Lab # 1 Voting machine Watch lecture on ePD (video) + ePD_Demo + Prelab for Lab # 3 Week 3 Jan. 29-Feb 1 Lab # 3 Intro. to Electronic Product Designer (ePD) Week 4 Feb. 5-8 Lab # 5 Debugging via simulation using ePD Introduction to FPGAs Prelab for Lab # 6, also perform steps 6.1 and 6.2 of the procedure and complete the “core” of the DETOUR design and simulate. Install Xilinx and ModelSim on your Home PC Week 5 Feb. 12-15 Lab # 6, Lab #7 Implementation of Detour signal lab on the FPGA board Lab 7: Number lock (Try to finish Number Lock in lab)
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This note was uploaded on 05/13/2008 for the course EE 201L taught by Professor Puvvada during the Spring '08 term at USC.

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