homework7-solutions - CprE 381 Computer Organization and...

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CprE 381 – Computer Organization and Assembly Level Programming Fall 2013 Homework #7 Assigned: Friday Oct 19 Due: Friday Oct 25, Midnight Notes: Do this week’s reading before you start on the homework. Complete the assignment electronically and submit it on BlackBoard Learn. Late homework is accepted within three days from the due date. Late penalty is 10% per day. 1. Different execution units and blocks of digital logic have different latencies (time needed to do their work). In Figure 4.2 there are seven kinds of major blocks. Latencies of blocks along the critical (longest-latency) path for an instruction determine the minimum latency of that instruction. Assume the following resource latencies. Answer those questions for both settings of latencies . I-MEM Add Mux ALU Regs D-Mem Control I. 400ps 100ps 30ps 120ps 200ps 350ps 100ps II. 500ps 150ps 100ps 180ps 220ps 1000ps 65ps a. [5] What is the critical path for a MIPS AND instruction?
Grading : Give appropriate partial credit. -1 if Regs appears only once. b. [5] What is the critical path for a MIPS load word ( LW ) instruction? I. The critical path is I-Mem, Regs (read), Mux, ALU, D-Mem, Mux (write). II. The critical path is I-Mem, Regs (read), Mux, ALU, D-Mem, Mux (write). Note: Same as above. Grading : Give appropriate partial credit. -1 if Regs appears only once.

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