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Unformatted text preview: Clock-to-Q delay is .15 ns, how soon after the D input changes to its final value can we be guaranteed to see a valid Q output? 7. (5%) Give a rule about inputs changing in a dynamic gate. 8. (5%) What is the final output of a dynamic gate during precharge? 2 2 9. (10%)A compound gate is shown below. Convert this gate to dynamic logic. 10. (10%) A positive edge-triggered D flipflop has a setup time of .2 ns, a hold time of .1 ns, a clock-to-Q delay of .22 ns, and is being clocked with a frequency of 950 MHz. How much combinational delay can be tolerated between flipflops and still have correct circuit operation? 3 3...
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This note was uploaded on 04/16/2009 for the course EE 477 taught by Professor Parker during the Spring '09 term at USC.
- Spring '09