Lecture04_MOS_Small_Sig_2up

Lecture04_MOS_Small_Sig_2up - EECS240 Spring 2008 Lecture...

Info iconThis preview shows pages 1–6. Sign up to view the full content.

View Full Document Right Arrow Icon
EECS240 – Spring 2008 Lecture 4: Design-Driven Small Signal Models Elad Alon Dept. of EECS EECS240 Lecture 4 2 MOSFET Models for Design SPICE (BSIM) For verification Device variations Hand analysis Velocity-sat model (good mostly for intuition) Small-signal model Challenge How to accurately design when hand analysis models may be way off?
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
EECS240 Lecture 4 3 Parameters Designers Care About Layout designer: Mostly care about just W and L Circuit designer: Gain Æ g m , r o Bandwidth Æ g m , C GS , C GD , … Power Æ I D Voltage swing Æ minimum V DS Noise Can get many of the circuit parameters without resorting to BSIM Or rather, by just using BSIM as a look-up table EECS240 Lecture 4 4 Low Frequency Model 1 st order Taylor expansion of I D : Just need to know the coefficients…
Background image of page 2
EECS240 Lecture 4 5 V od Square Law Model In saturation: EECS240 Lecture 4 6 Weak Inversion g m In weak inversion we have bipolar behavior Good model if transistor is actually used in weak inversion
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
EECS240 Lecture 4 7 Transconductance weak inversion strong inversion ( - V T ) EECS240 Lecture 4 8 Transconductance (cont) Compare g m of MOSFET and BJT: Since V od >> V t , BJT has larger g m for same I D Why can’t we make V od ~ V t ? You can – if you work in subthreshold Gives great g m per unit current But pay a penalty in speed (will see shortly) V od
Background image of page 4
EECS240 Lecture 4 9 Output Resistance r o Hopeless to model this with a simple equation (e.g. g ds = l I D ) EECS240 Lecture 4 10 Open-loop Gain a v0 Represents maximum attainable gain from a transistor May be more useful than r o Simulation Notes: Bias current i dc sets V GS -V T
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 6
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 05/23/2008 for the course EECS 240 taught by Professor Eladalon during the Spring '08 term at University of Calgary.

Page1 / 17

Lecture04_MOS_Small_Sig_2up - EECS240 Spring 2008 Lecture...

This preview shows document pages 1 - 6. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online