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Midterm1F03-01

Midterm1F03-01 - EE 307-01 F03 MIDTERM EXAM#1 Braun CLOSED...

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Unformatted text preview: EE 307-01 F03 MIDTERM EXAM #1 Braun CLOSED BOOK + 1 Cheat Sheet State assumptions and show work. (1 point) Print Your Name: 5621 MT/fl/f/j No unauthorized help given or received. I will not discuss this exam with another student until after 1:00 today. (l point) Si gnature: é/Vflm Unless stated otherwise please use the following transistor parameters for ALL problems: er V P0: 0.5 v km: 40 “AN kp’/2= 20 uA/V‘ i: o v -2¢,.~= 0.6 v, andy= 0.4 v“? Assume that body connections of all NMOS transistors are grounded and PMOS bodies go to +VDD. 1. Saturated Enhancement NMOS inverter with VTC shown to the right. 2.5 (3 points) A) Determine the value of VOH for this inverter. 2.0 14H ; .2, 9V 5 11.5 8 A l 0 (3 points) B) Determine the value of V01 for this inverter. . 0.5 l/I’n 3:” 5721/ nnix...“..1....1....|....1.=1 vr/L, U.U 0.0 05101.5 2.0 25 V [V]ir (6 points) C) Draw the circuit diagram for this saturated enhancement load inverter. Clearlv label the nameo ea achc component, clearly label each signal line and clearly specify the value(s) of any voltage source(s). . VD” W/P‘Lf/Z/ V10” 1 [6% ' FF. .. v 4 - . j l M; 16:2 = Vim/a * [1 ”OW/2% 5/44 \ , V2 14w— 2 0» 1’ 7 MW [Lifi/téél/ , way LL, 1 .- ,. C . r 1/” : 14.; y 24, :251/ #4415174V . 3 .5 71/ (5 points) D) Specify the size(s) of any transistors in the inverter. . 2 Q I i/m :- 12 2v 476410195 W777 M2 5/47) ”5 4/47 f' ” ‘2' I; : :K/Ll/ )[Zéah' {Tl/)Vé: L52"? '\ Z J/ 1 “7/ [if _ / V72: lr/Vai'afl[,iiupw‘/2 ;/M , v a? 9.2. (4,4157, M7 . , :2 fl 5%? V d 5] ) . , ' 4 ,_ / j V ~ .‘L/tl hr; M in; » a. a . ' I 1/ I (LU/4)} 2190a ”LN)V 'DL 5:; 2(2 2 V 5? 91 [/2 ( ,xc'if (id/4),; : 1/] j [aw/4,), : 2/5// ,.-u , __ —_ —— __ Part 2 (section —0 1) 2. CMOS inverter propagation delay. The inverter drives a load capacitance, CL = 10 pF. VDD = 4'0 V Use VTN= — VTP = 0.5 v, kN= 2 uA/V2 and kp = 5 uA/Vz. (4 points) A) Determine the power dissipation in transistor Mp, at a time tpLH after the appropriate P Vow rail-to-rail voltage swing on the input signal, VIN. VIN WI 5 “9‘ :0 V N ICL - 117.1129 -. Kay « ,zfl/ OPF ”in” " i 2, ' y. " _ ”if ,15 4M4 /'///V /5 57;; . 4 . 7 Z 7?) 7; A” I V5574 7" Kw) l/giflfl "' Liv/7] , fl 1 T 7 Z _, L 9 r 7 . l/ 7,. 979m" 2 l/ : Maw/V / [a “1/ ' $25M , 1- (4 points) B) Estimate the value of tPLH. I97 23:6’* My 5 ”5L :ay : Iii/r i/in /,§ @2177“ 11/1; ,1 § {2/375 ' Ir / I / I Ily / 1/ fl 4 t v ‘ ,7 a ._, ' p / ' _ . If) : K/[l/ng 7L #7,») : >/é§/§“ 'QS’y I 5/, 25::(//2 I47 f: 024/; If : Siva/7?" ()le (Hilfigffl ,UZ/ WW7 // -__»- 7 -’ .4“..._ __, ,'/}Z Iflv’ ; §[v///‘:} 'f J/[jgjfig/g 25425;”? fglifléf‘y- 5§éfl 7v 5 dilly /£7 Fr Zl” W _7 _7777,.7 : ~-——————-—-<i; : 3m; J’fl’l/f :)>/fi5/If ’/ ‘ (3 points) C) Circle and cross out the necessary words to make the following sentence true: Doubling the width of transistor M p would W/Jea—veanehafiged /@ the value of [PL/.1. Explain why. \F” 7‘Lt/ ”9 7K2 ‘7 wififlw (3 points) \/ 0M7 (3 points) (4 points) Part 3 (section —01) {3 3. NMOS and CMOS logic gates. ‘1'“ A) For the NMOS gate to the right, write a Boolean expression for the logic function obtained at Vour- : $251+ 0'5 +/-*)eg; _l_§ . Y} il l e la .3. 1; IF— 7% I Q be _l_a _|_$ m L.___l B) Assume that y = 0.4 VI/Z. Please list the name(s) of any transistor(s) in the NMOS gate to the right in which the body effect could influence its operation. Gd 74/ 5/ 5/ £115 F _4__ iii—El} C) Draw the circuit diagram for a CMOS gate that produces the same logic function as the above NMOS gate. mil End l ...
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