# Prelab10Upload - Objectives I will be introduced to new...

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Objectives: I will be introduced to new techniques that exist for binary addition, like carry-lookahead addition. I will learn how to design the necessary components using a mixture of dataflow and structural Verilog. Then I will simulate the circuit using Xilinx ISE. I will reinforce the concepts discussed in lecture with this hands-on experience. Design: For this pre-lab, we were asked to provide: 1. Describe the Generate/Propogate Unit, Carry-Lookahead Unit, and the Summation Unit with dataflow Verilog. /* This module describes the Carry Generate/Propagate Unit for 4bit carry-lookahead addition*/ module generate_propagate_unit(G, P, X, Y); //ports are wires as we will use dataflow Output wire [3:0] G, P; Input wire [3:0] X, Y; Assign G[3] = X[3]&Y[3]; Assign G[2] = X[2]&Y[2]; Assign G[1] = X[1]&Y[1]; Assign G[0] = X[0]&Y[0]; Assign P[3] = X[3]^Y[3]; Assign P[2] = X[2]^Y[2]; Assign P[1] = X[1]^Y[1]; Assign P[0] = X[0]^Y[0]; endmodule ///////////////// This study resource was shared via CourseHero.com

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