Sequential Circuits - Objective: Design, construct and test...

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: Design, construct and test synchronous sequential circuits. Procedure: Up-Down Counter with Enable In the first part of this lab we designed, constructed and tested a two-bit counter that counts up or down. An enable input E is used to determine whether the counter is on or off. When E=0 the counter is disabled and remains at its present count even though clock pulses are applied to the flip-flops. When E=1 the counter is enabled and a second input, x, determines the direction of the count. If x=1, the circuit counts upward and if x=1 the circuit counts downward. We configured a state diagram (Diagram 8.2) for these requirements and from this determined the state table (Table 8.1) and the excitation table (Table 8.2). It was then from this we formulated a map to determine the functions that would enable this circuit (Map 8.1). The logic diagram for this circuit is shown below in Diagram 8.2. Diagram 8.1
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This note was uploaded on 06/06/2008 for the course ECE 282 taught by Professor Lozwoski during the Spring '08 term at Southern Illinois University Edwardsville.

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Sequential Circuits - Objective: Design, construct and test...

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