w05-quiz4-solutions

w05-quiz4-solutions - ECE 30 Introduction to Computer...

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ECE 30 Introduction to Computer Engineering Quiz 4 March 2, 2005 Name Solution Student ID Signature Your score out of 1 15 2 2 3 3 Total 20
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Mem Reg File A B ALU PC SE << 2 IR MDR ALUOut A D in D in 4 << 2 PCSrc IorD MemRd MemWr IRWr RegDst MemtoReg PCWr PCWrCond RegWr ALUSrcA ALUSrcB ALU ctrl ALUOp 0 1 2 3 0 1 0 1 0 1 0 1 0 1 2 IR[25:0] PC[31:28] IR[15:0] IR[15:11] 28 2 4 2 16 32 zero Shown above is a multi-cycle CPU. There are six registers in this datapath: PC , IR , MDR , A , B , and ALUOut . Of these, PC and IR are enabled to change when PCWr and IRWr are high (logic “1”) respectively. These control signals change shortly after the sampling (rising) edge of the clock, as the control-FSM changes its state. Therefore, the outputs of these registers do not change until the next sampling edge of the clock after the enabling control signals are asserted, as shown in the following timing diagram. In clock Out en D Q Out In clock 32 32 PC PCWr 08000000 08000004 08000000 08000004 PCWr 2
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This note was uploaded on 06/09/2008 for the course ECE 30 taught by Professor Gert during the Spring '08 term at UCSD.

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w05-quiz4-solutions - ECE 30 Introduction to Computer...

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