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CS 320 Unit 5 Primary Memory - CS 320 Computer Architecture...

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CS 320 Computer Architecture Unit 5 Primary Memory Spring 2008 Furman Haddix, Ph.D. Assistant Professor Minnesota State University
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Unit 5 Primary Memory Objectives Latches SR, clocked SR, clocked D Flip-flops D rising edge, D falling edge Main Memory Cell size is number of bits stored in cell Size of cell determines number of data lines needed Number of cells on chip determines number of low-order address lines Number of chips determines number of high-order address lines Number of functions and number of peripherals determine number of control lines Buffers Cache (Split, Unified) Math Memory Hierarchy Memory Chips Types of Memory SRAM, DRAM, ROM, PROM, EPROM, EEPROM, Flash
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Latches Latches are one way of storing values Latches covered SR (Set-Reset) clocked SR clocked D (Data) A Latch is level triggered; this makes the latch transition speed dependent on the duration of the high portion of the clock signal
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R 1 S 1 0 0 0 0 1 1 1 1 0 0 Latch is implemented using NOR Gates. SR SR Note: The SR latch has only two states (Set: Q = 1; Reset: Q = 0).
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1 1 0 0 1 1 1 0 1 0 0 0 1 0 1 0 1 0 1 0
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1 0 1 0 1 1 0 0 1 0 1 0 0 1 1 0 0 0 1 1
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Flip-flops Like latches, flip-flops are a way of storing values Flip-flops covered D rising edge D falling edge Flip-flop is edge triggered; this makes the flip-flop transition speed dependent on the transition time of the signal
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C K Signal Inversion plus Propagation Delay CK CK C K AND(CK, CK)
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High-signal Latch Low-signal Latch Rising-edge Flip- flop Falling-edge Flip-flop Execution Sequence in Response to Cycling Signal: HL, FF, LL, RF, HL, FF, LL, RF, HL, FF, LL, RF, HL High-signal Latch Low-signal Latch Rising-edge Flip- flop Falling-edge Flip- flop CK
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Common Power Source and Sink Connections Not Shown Two Independent D Flip-flops Eight D Flip-flops with common Clock and Clear controls What kind of Flip-flops? Register Rising Edge Falling Edge What is a possible use of the MSI?
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Example Main Memory using Flip-Flops D Flip-flops hold bit values Data lines into memory One for each bit in cell to/from bus From/to each flip-flop in memory cell Address lines Low order portion decodes cell in memory chip High order portion selects memory chip Control lines Determine operation, e.g., load, store
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Decode of high-order address bits Decode of control lines low-order address bits Data In and Data Out are same lines on bus ASSUMPTION: Words and Cells are same size.
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