CS 320 Unit 5 Primary Memory

CS 320 Unit 5 - CS 320 Computer Architecture Unit 5 Primary Memory Spring 2008 Furman Haddix Ph.D Assistant Professor Minnesota State University

Info iconThis preview shows pages 1–13. Sign up to view the full content.

View Full Document Right Arrow Icon
CS 320 Computer Architecture Unit 5 Primary Memory Spring 2008 Furman Haddix, Ph.D. Assistant Professor Minnesota State University
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Unit 5 Primary Memory Objectives Latches SR, clocked SR, clocked D Flip-flops D rising edge, D falling edge Main Memory Cell size is number of bits stored in cell Size of cell determines number of data lines needed Number of cells on chip determines number of low-order address lines Number of chips determines number of high-order address lines Number of functions and number of peripherals determine number of control lines Buffers Cache (Split, Unified) Math Memory Hierarchy Memory Chips Types of Memory SRAM, DRAM, ROM, PROM, EPROM, EEPROM, Flash
Background image of page 2
Latches Latches are one way of storing values Latches covered SR (Set-Reset) clocked SR clocked D (Data) A Latch is level triggered; this makes the latch transition speed dependent on the duration of the high portion of the clock signal
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
R 1 S 1 0 0 0 0 1 1 1 1 0 0 Latch is implemented using NOR Gates. SR SR Note: The SR latch has only two states (Set: Q = 1; Reset: Q = 0).
Background image of page 4
1 1 0 0 1 1 1 0 1 0 0 0 1 0 1 0 1 0 1 0
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
1 0 1 0 1 1 0 0 1 0 1 0 0 1 1 0 0 0 1 1
Background image of page 6
Flip-flops Like latches, flip-flops are a way of storing values Flip-flops covered D rising edge D falling edge Flip-flop is edge triggered; this makes the flip-flop transition speed dependent on the transition time of the signal
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
C K Signal Inversion plus Propagation Delay CK CK C K AND(CK, CK)
Background image of page 8
High-signal Latch Low-signal Latch Rising-edge Flip- flop Falling-edge Flip-flop Execution Sequence in Response to Cycling Signal: High-signal Latch Low-signal Latch Rising-edge Flip- flop Falling-edge Flip- flop CK
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Common Power Source and Sink Connections Not Shown Two Independent D Flip-flops Eight D Flip-flops with common Clock and Clear controls What kind of Flip-flops? Register Rising Edge Falling Edge What is a possible use of the MSI?
Background image of page 10
Example Main Memory using Flip-Flops D Flip-flops hold bit values Data lines into memory One for each bit in cell to/from bus From/to each flip-flop in memory cell Address lines Low order portion decodes cell in memory chip High order portion selects memory chip Control lines Determine operation, e.g., load, store
Background image of page 11

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Decode of high-order address bits Decode of control lines low-order address bits Data In and Data Out are same lines on bus ASSUMPTION: Words and Cells are same size.
Background image of page 12
Image of page 13
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 06/09/2008 for the course CS 320 taught by Professor Furmanhaddix during the Spring '08 term at Minnesota State University, Mankato.

Page1 / 35

CS 320 Unit 5 - CS 320 Computer Architecture Unit 5 Primary Memory Spring 2008 Furman Haddix Ph.D Assistant Professor Minnesota State University

This preview shows document pages 1 - 13. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online