CS 320 Unit 6 Example Microarchitecture

CS 320 Unit 6 Example Microarchitecture - CS 320 Computer...

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CS 320 Computer Architecture Unit 6 Example Microinstruction Architecture Furman Haddix, Ph.D. Assistant Professor Minnesota State University Spring 2008
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Micro- architecture Level
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Unit 6 Microinstruction Architecture Objectives The functionality of a simple (Mic-1) microarchitecture Data Path Control 16 Operations on 2 Operands Memory Control Data, Instructions Controlling the microarchitecture through a microinstruction format Data Path Controls Write from C bus, Read to B bus, ALU/Shifter ops (2-bus architecture) Memory Controls Data Read/Write, Instruction Fetch Tanenbaum Chapter 4, Chapter 3 (ALU)
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Data Path of Mic-1 Data path The parts of the CPU primarily concerned with data, as opposed to control (instructions) Register File ALU (and Shifter) A Bus (Usually same as B bus – not present in Mic-1; in Mic-1 architecture, must take data from C bus via H register to access A port of ALU). B Bus (Register File to ALU B port) C Bus (ALU C port to Register File) Main Memory (Cache) interface to Register File
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Data Path of Mic-1 Register File 2 bits needed for three states: left/righ To D-Cache To/From D-Cache To I-Cache nitialized by Loader Memory Buffer Register (Instruction Register) Can be read as unsigned or signed H Register serves as A Input Register
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Data Path Register File MAR Memory Address Register Only register which communicates data addresses outside CPU MDR Memory Data Register Only register which communicates data values outside CPU PC Program Counter Only register which communicates instruction addresses outside CPU MBR Memory Buffer Register (or Instruction Register) Only register which receives instruction values from outside CPU SP Stack Pointer Maintains memory address for top of stack LV Local Variable (Frame Pointer) Maintains memory address for beginning of local variable frame CPP Constant Pool Pointer Maintains memory address for constant pool TOS Top Of Stack Maintains value of top of stack in memory OPC OPCode General purpose register. May be used to hold OpCode address for branch instructions H Holding A port Buffer, or General purpose register
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7 0 0 I 15 I 14 I 13 I 12 I 11 I 10 I 9 I 8 I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 1 I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 0 0 0 0 0 0 0 0 Mic-1 16-bit Shifter (8-bits left; 1-bit right) Shift Left Shift Right Right In Left Out Right Out Left In O i I i I 15 I 14 I 13 I 12 I 11 I 10 I 9 I 8 I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 O 15 O 14 O 13 O 12 O 11 O 10 O 9 O 8 O 7 O 6 O 5 O 4 O 3 O 2 O 1 O 0 0 I 15 I 14 I 13 I 12 I 11 I 10 I 9 I 8 I 7 I 6 I 5 I 4 I 3 I 2 I 1 1 Shift Left Shift Right O 15 O 14 O 13 O 12 O 11 O 10 O 9 O 8 O 7 O 6 O 5 O 4 O 3 O 2 O 1 O 0 0 0 I 15 I 14 I 13 I 12 I 11 I 10 I 9 I 8 I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 0 1 0 I 15 I 14 I 13 I 12 I 11 I 10 I 9 I 8 I 7 I 6 I 5 I 4 I 3 I 2 I 1 1 0 I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 0 0 0 0 0 0 0 0 1 1 Invalid Control Values
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Shift Left Shift Right O 15 O 14 O 13 O 12 O 11 O 10 O 9 O 8 O 7 O 6 O 5 O 4 O 3
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This note was uploaded on 06/09/2008 for the course CS 320 taught by Professor Furmanhaddix during the Spring '08 term at Minnesota State University, Mankato.

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CS 320 Unit 6 Example Microarchitecture - CS 320 Computer...

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