CS 320 Unit 8 Macroarchitecture Implementation

CS 320 Unit 8 Macroarchitecture Implementation - CS 320...

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CS 320 Computer Architecture Spring 2008 Unit 8 IJVM Implementation on Mic-1 Furman Haddix, Ph.D. Assistant Professor Minnesota State University
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Unit 8 Objectives Mic-1 microinstruction architecture employs a 16- operation ALU and uses shifter, buses and registers Mic-1 can be used to implement the IJVM ISA The IJVM ISA is implemented by mapping each instruction to a location in the control store The instruction implementation is addressed by the control store address For each assembly language instruction, there is an instruction set architecture instruction. For each ISA instruction, there are one or more microinstructions, expressible in Micro Assembly Language (MAL) or 36-bit forms. MAL is an RTL-like language Translation from MAL to 36-bit form is one-to-one.
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The Mic-1: An Example Micro- Architecture, Figure 4-6 MAR - Memory Address Regist MDR - Memory Data Register PC - Program Counter MBR - Memory Buffer Register MBRU - MBR (unsigned) * Note two control signals SP - Stack Pointer LV - Local Variables CPP - Constant Pool Pointer TOS - Top of Stack OPC - OPCode (temporary) H - Holding Pointer Datapath Control Unit 9 Machine Languag e Instructi on Control Store Address is Start of Microfunction Microinstructi on sequence is loaded in sequence into MicroInstructi on Register from Control Store Control Signals are propagated throughout Datapath OpCode is Address into Control Store
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Micro Assembly Language MAL is a high-level Micro Assembly Language In MAL, each cycle is one line. The real Microassembly Language (36-bit format) represents the control line encoding necessary to execute microinstructions. In the last unit we looked at IJVM, which is actually a Java assembly language (or intermediate form). In the last unit we looked at the real instruction set, or machine language; in this unit we will look at the microinstruction language implementation of the machine language.
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More on MAL (RTL) The Real Stuff MAL (Abstract) IJVM (Abstract ISA) Java 36 bit instructions in Control Store One layer removed Called ISA but looks like an assembler or an intermediate form Translation (compile or interpret) to IJVM (or JVM) Conceptual Path Java IJVM-JASMIN Assembly MAL L5 L4 L2.5 Physical Path Java JVM - bytecode Microinstructions (36-bit) ISA Machine Language L4 L5 L3 L2 H H H H M M M = H = Human-friendly M = Machine-friendly H = Human-friendly M = Machine-friendly H = Human-friendly
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Mic-1 Permitted Operations DEST is any C Bus Destination SOURCE is any B Bus Source H is the A input register for the ALU This is used to assemble wide operands
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Comparing Figures 4-2 and 4-16 The ALU results of 4-2 mirror the possible operation results of 4-16 DEST = Value put onto C bus from ALU SOURCE = Value taken from B bus H = Register used in place of A bus
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Recall Figure 4-1 DEST = Value put onto C bus from ALU SOURCE = Value taken from B bus H = Register used in place of A bus
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CS 320 Unit 8 Macroarchitecture Implementation - CS 320...

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