CS 320 Unit 9 Improving Microarchitecture Performance

CS 320 Unit 9 Improving Microarchitecture Performance - CS...

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CS 320 Computer Architecture Unit 9 Improving Microarchitecture Performance Spring 2008 Furman Haddix, Ph.D. Assistant Professor Minnesota State University, Mankato
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Unit 8 Improving Microarchitecture Performance 2 Unit 9 Objectives Compare Design Rationale of Mic-1 with Faster Alternatives used in Mic-2 Remove decoder to speed execution Reduce interpreter loop with microcode Three bus architecture enhances operand fetch Instruction fetch unit Fetch in parallel with datapath operations IMAR and SR decouple fetch from execute MBR2 buffer for “WIDE” offsets Fetch words rather than bytes Increment IMAR and PC outside of ALU
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Unit 8 Improving Microarchitecture Performance 3 Ways to Improve Mic-1 Performance Remove Bus B Register Decoder Remove layer of hardware, but add five bits to control store instructions Add five bits to microinstruction format width • Rewire B Bus control lines Overlap interpretation loop with other microinstructions (where possible) Reduces length of many microfunctions if fetch call included Increases overall length of microprogram more total microinstructions overlap not possible in all microfunctions Rewrite each microfunction Add a second ALU input bus (one cycle for two input operand operations) Add in bus hardware Add ten bits to control store and microinstruction format for A Bus Control and 1 bit so that B Bus can read from H register, making H a general purpose register Rewrite each microfunction Add an Instruction Fetch Unit Design of new hardware component Rewrite each microfunction Last three enhancements require only one microprogram rewrite
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Unit 8 Improving Microarchitecture Performance 4 Removing B Bus Register Decoder 512 x 41 bit control store for the microprogram 9 Before After
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Unit 8 Improving Microarchitecture Performance 5 Overlap Interpretation Loop with Microfunctions Rewrite POP microfunction pop execution in Mic-1 pop execution in Mic-2
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Unit 8 Improving Microarchitecture Performance 6 Adding a Second ALU (A) Bus In Mic-1: LHS register(s) is write from C Bus; a RHS register is H or
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CS 320 Unit 9 Improving Microarchitecture Performance - CS...

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